Quadrature-Clock And Direction Decoding - Texas Instruments TMS320F28004x Technical Reference Manual

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QA
QB
QCLK
QDIR
QPOSCNT +1 +1
QA
QB
QCLK
QDIR
QPOSCNT −1 −1 −1 −1 −1 −1
Phase Error Flag— In normal operating conditions, quadrature inputs QEPA and QEPB will be 90
degrees out of phase. The phase error flag (PHE) is set in the QFLG register and QPOSCNT value
can be incorrect and offset by multiples of 1 or 3, when edge transition is detected simultaneously
on the QEPA and QEPB signals to optionally generate interrupts. State transitions marked by
dashed lines in
Count Multiplication— The eQEP position counter provides 4x times the resolution of an input clock by
generating a quadrature-clock (QCLK) on the rising/falling edges of both eQEP input clocks (QEPA
and QEPB) as shown in
Reverse Count— In normal quadrature count operation, QEPA input is fed to the QA input of the
quadrature decoder and the QEPB input is fed to the QB input of the quadrature decoder. Reverse
counting is enabled by setting the SWAP bit in the QDECCTL register. This will swap the input to
the quadrature decoder thereby reversing the counting direction.
19.4.1.2 Direction-count Mode
Some position encoders provide direction and clock outputs, instead of quadrature outputs. In such cases,
direction-count mode can be used. QEPA input will provide the clock for position counter and the QEPB
input will have the direction information. The position counter is incremented on every rising edge of a
QEPA input when the direction input is high and decremented when the direction input is low.
SPRUI33 – November 4 2015 – Revised January 2017
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Figure 19-7. Quadrature-clock and Direction Decoding
+1 +1 +1 +1 +1 −1 −1
−1 +1 +1 +1 +1 +1 +1
Figure 19-6 are invalid transitions that generate a phase error.
Figure 19-7 .
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−1 −1 −1 −1 −1 −1 −1 −1
+1 +1 +1 +1
Quadrature Decoder Unit (QDU)
−1 +1 +1 +1
+1 −1 −1 −1
Enhanced QEP (eQEP)
1789