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2. ICU PWB
(1) CCD control section
Basic functions
1
Generation of the timing signal to the lens unit CCD drive PWB.
2
Process of the analog signal from the lens unit CCD drive PWB,
and the A/D converting section.
3
Shading correction/signal control process
Clamp
Peak
A
circuit
B
hold
C
E
CCD
Clamp
Hold
Lens
drive
pulse
reset
unit
PWB
Clamp
Peak
circuit
hold
Operational description
The CCD image signal output pins of two system (ODD, EVEN) for
one line to allow high-speed process.
The output signals from the output pins are separately processed in
defferent circuits as described below before being sent to the PCU.
The impedance of the CCD signal
PWB (lens unit) is converted and sent to the clamp circuit, where the
black level is clamped to 2.7V at the timing of the CLMP signal
B
the analog switch
.
D
The analog signal
which was clamped is sent to the FIFO memory
after AD conversion. The peak hold is reset by the VRST signal
every pixel.
A
0V
B
2.7V
0V
C
D
E
F
1line
A/D
D
conversion
F
CCD data
Shading D/A
FIFO
image process
Shading D/A
section
A/D
conversion
A
amplified by the CCD drive
1line
In the A/D conversion, by turning off the shading correction data, the
CCD element fluctuation and the optical system (lamp, lens) light
quantity fluctuation are corrected, and the analog data are converted
into 8-bit digital data between the white level and the black level.
The 8-bit image data converted in the even and the odd circuits are
stored in FIFS by one pixel at one time alternately.
These data are taken out sequentially to output the image data of one
array to the image process section.
5150 pixel CCD linear sensor (Monochrome)
(Outline)
The ILX510 is two-output system reduction type CCD linear sensor,
which scans an A3 Document in 400 dpi.
(Features)
•
Number of effective pixels: 5150 pixels
•
Pixel size:
•
Max. data rate:
•
Power voltage:
•
All input clocks:
(Absolute max. rating)
•
Power voltage:
C
by
VOUT-ODD
E
for
∅RS-ODD
∅LH-ODD
∅2-ODD
∅1-ODD
9 – 2
7 µm × 7 µm (7 µm pitch)
40MHz
12V U1 battery
CMOS 5V drive
VDD 15V
Pin arrangement (Top view)
N C
1
22
GND
VGG
2
1
21
GND
3
20
VOUT-EVEN
GND
4
19
VDD
∅RS-EVEN
5
18
∅LH-EVEN
6
17
N C
7
16
N C
GND
8
15
N C
∅2-EVEN
9
14
∅1-EVEN
10
13
5150
∅ROG
VDD
11
12
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