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[MTF correction]
When the characteristic value outputted from gate array B is inputted
to the address of multi-function LUT, data which show the charac-
teristics of the peripheral pixels are outputted from the multi-function
LUT. For example, the data show that the pixel and the peripherals
are characters and edged of line drawing or that they are part of a
hatched image of photo in a newspaper or that they are part of a
photo of continuous gradation (that is not a hatched photo). Filter
process is performed according to each pixel's characteristics.
[Gamma correction/line alignment/black-white highlight]
After the MTF correction, the image is subject to the gamma correc-
tion in order to cope with the OPC drum characteristics, the develop-
ing characteristics, and the actual copy density. Before copying, the
CPU reads the density conversion look up table value corresponding
to the value which was set by the user with the density adjustment
key from the EPROM (data), and writes the data into the gamma
correction LUT (SRAM). The image data are connected to the lower 8
bits of the gamma correction LUT address and converted by the look
up table. Black-white highlight is performed at the same time.
[Soft photo mode]
This is the multi-value dithering mode which has been newly added
from this mode. The area gradation is combined with the pulse width
modulation to improve the gradation of photo. The size of area grada-
tion (dither matrix) can be selected with simulation.
[Self printing mode]
Gate array B prints out the test pattern by outputting the address
count values of main scanning and sub scanning.
Gate array A
Pin arrangement table
No.
Pin name
I/O
1
GND
2
RAMADR0
O
Data bus to the peripheral memory
*
*
*
connected to this LSI.
7
RAMADR5
O
8
VDD
9
RAMADR6
O
Data bus to the peripheral memory
connected to this LSI.
10
RAMADR7
O
11
GND
Data bus to the peripheral memory
12
RAMADR8
O
connected to this LSI.
13
GND
14
VDD
15
RAMADR9
O
Data bus to the peripheral memory
*
*
*
connected to this LSI.
20
RAMADR14
O
Signal which shows the end of shading
21
FINAL
O
correction.
22
GND
23
RAMADR0
I/O
Address bus to the peripheral memory
*
*
*
connected to this LSI.
30
RAMADR7
I/O
31
GND
32
XIFDAT0
I/O
*
*
*
Data bus to set the built-in register.
42
XIFDAT7
I/O
43
GND
44
SHADOUT0
I/O
Signal to output the data after shading
*
*
*
correction.
53
SHADOUT7
I/O
54
GND
Function
1 – 9
No.
Pin name
I/O
55
XIFADR0
IN
*
*
*
Data bus to set the built-in register.
60
XIFADR5
IN
61
RAMRD
OUT Read signal to the peripheral memory.
62
VDD
63
GND
64
WCLK
OUT Not used.
System clock of this LSI. Clock of
65
CLK1
IN
16MHz is inputted.
Data enable signal to the built-in
66
XIFEN
IN
register.
67
XIFRD
IN
Data read signal to the built-in register.
68
XIFWR
IN
Data write signal to the built-in register.
69
RESET
IN
Initializes the LSI.
70
VDD
System clock of this LSI. Clock of
71
CLK2
IN
16MHz is inputted.
72
RAMWR
OUT Write signal to the peripheral memory
73
HSYNC
IN
Image data 1 line read start signal.
Signal which shows the effective area
74
PAGE
IN
of one page of image data.
75
RESERVE
76
RESERVE
Not used.
77
RESERVE
78
RESERVE
79
GND
80
RESERVE
81
RESERVE
Not used.
82
RESERVE
83
RESERVE
84
GND
85
H0
OUT
*
*
*
Not used.
87
H2
OUT
88
VDD
89
GND
90
V0
OUT
*
*
*
Not used.
92
V2
OUT
93
ADIN0
IN
*
*
*
Image data bus
100
ADIN7
IN
Function
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