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EN 56
8.
Q522.1HE LA
8.3
Diagram B03B, TDA10048HN (IC7T17-1)
Block Diagram
ANALOG
VIM
ADC
VIP
PLL
XIN
OSCILLATOR
XOUT
SCL_TUN
SDA_TUN
2
I
C-BUS
INTERFACE
SCL, SDA
SADDR
ΣΔ
ΣΔ
GPIO[3:0]
ΣΔ
ΣΔ
MPEG-2
MPEG TS
OUTPUT
DO[7:0]/S_DO
INTERFACE
(parallel/serial)
Pin Configuration
2009-Dec-04
IC Data Sheets
ΣΛ
STEP INTERFACE
DUAL
AGC
ΣΛ
STEP INTERFACE
DIGITAL
FFT
AGC
2K / 4K / 8K
CARRIER
TIME
RECOVERY
RECOVERY
TDA10048HN
DSP CORE SYNCHRONISATION
FREQUENCY, TIME, FRAME RECOVERY
FFT WINDOW POSITIONING
TPS DECODING
DE-
RS
FORNEY
SCRAMBLER
DECODER
INTERLEAVER
C
P
T
_
U
N
C
O
R
terminal 1
index area
1
V
DDA(ADC)(3V3)
I V
M
2
V
P I
3
V
4
SSA(ADC)
5
V
DDD(ADC)(3V3)
6
V
SSA(OSC)
TDA10048HN
X
N I
7
X
O
U
T
8
V
9
DDA(OSC)(1V2)
10
V
SSA(PLL)
V
11
DDA(PLL)(1V2)
V
12
DDDC(1V2)
Transparent top view
Figure 8-3 Internal block diagram and pin configuration
AGC_TUN
AGC_IF
DIGITAL FRONT-END
AND OFDM
DEMODULATION
DYNAMIC
CCI
TIMESHIFT
CANCELLER
COARSE
ACI
TIME
FILTERING
ESTIMATOR
OUTER
VITERBI
DE-
DECODER
INTERLEAVER
V
B
E
R
C
B
E
R
36
TRST_N
35
S
C
34
S
D
33
SADDR
32
GPIO0
31
V
DDDC(1V2)
30
V
SSDC
29
V
SSD
28
V
DDD(3V3)
27
DO7
26
DO6
25
DO5
CHANNEL ESTIMATION
AND CORRECTION
PARTIAL
CPE
CHANNEL
CALCULATION
ESTIMATION
TIME
INTERPOLATION
FREQUENCY
INTERPOLATION
CONFIDENCE
CHANNEL
CALCULATION
CORRECTION
confidence
INNER
BIT
FREQUENCY
DE-
DEMAPPER
DE-
INTERLEAVER
CHANNEL DECODER
L
A
(I,Q)
H_16800_127.eps
090507
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