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5-2-9 CIS Input Processor
To process the B/W input signal, maximum
(+V
) and minimum (-V
REF
input signal are controlled by calibrating MUXA
and MUXB in the high state for the maximum
level, and setting them to earth for the minimum
level.
CPUCLK
Timing & Control
5-2-10 CIS Driver
The CIS driver clock frequency is 500 kHz. A low
duty cycle of 50% is used to lengthen the charging
CLOCK
SI
SIG
SF700AT
) values of the CIS
REF
Dither & Shading
Correction
Tables
Scanner Image
Processing
6-bit FADC
Scanner
Figure 5-9: Scanner Interface Block Diagram
500 KHZ (L:DUTY 50 %)
1 LINE
Figure 5-10: CIS Driver Clock Timing
Processing to compensate for CIS shading
distortion is controlled with MUXA 'low' and
MUXB 'high'. For B/W mode, MUXA should be
'high', and MUXB 'low'. For half-tone, MUXA is
'low', and MUXB is 'high'.
XFC-B
External Circuits
Shading RAM
External
Line Buffer
Processing
-Vref
+Vref
Vin
VIDCTL(1:0)
Start, CLK1.
CLK1n, CLK2
time. A start signal is provided every 5 ms to
match the line scanning time. Actual image signal
is provided in less than 4.1 ms, using the 500 kHz
clock and taking B4 paper size into consideration.
Circuit Description
RAM
RAM
Video
+
-
Scanner
Drivers
5-7
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