Sony DSR-1500 Service Manual page 12

IC
CXD3107R (SONY)
C-MOS AUDIO REC/PB SIGNAL PROCESSOR
—TOP VIEW—
76 V
DD
77
78
79
80
81
82
83
84
85
86
87
88 GND
89
90
91
92
93
94
95
96
97
98
99
100
73
MUT
6
ERRF
15 A/D, D/A
NOIN
INTERFACE
14
DATI
BLOCK
12
DATO
11
LSBO
SELF-CHECK
BLOCK
RAM
RAM
INTERFACE
BLOCK
49
JRDY
50
JDAT
11-6
GND
GND
V
DD
PEAK LEVEL METER BLOCK
MUTING
MULT BUS
BLOCK
REC PB
BLOCK BLOCK
ADDRESS BUS
CXD3104R
INTERFACE
BLOCK
DATA BUS
CXD2912
CXD2913 MICROCOMPUTER
INTERFACE INTERFACE BLOCK
BLOCK
PIN
I/O SIGNAL
NO. NO.
1 — V
DD
2 I/O D7
3 I/O D6
4 I/O D5
5 I/O D4
50 6 O ERRF
49
7 I LRCI
48 8 I BCKI
47 9 O LRCO
46
10 O BCKO
45 11 O LSBO
44
12 O DATO
43 13 — GND
42
14 I DATI
41 15 I NOIN
40 16 O DSPO
ATC
39
17 O
38 18 O ATLT
37
19 I TCK
36 20 I TENA3
35
21 I TDI
34 22 I TENA1
33 23 O TDO
32
24 I TRST
31 25 I VST
30
29
28
27
26
INPUT
ACF
: MICROCOMPUTER FRAME COMMUNICATION CHIP SELECT
ACT
: MICROCOMPUTER TRACK-PAIR COMMUNICATION CHIP SELECT
ATT
: AUTO ATT INTERFACE CHIP SELECT
BCKI : 64 FS SIGNAL
DATI : AUDIO DATA
DSP
: ADSP INTERFACE CHIP SELECT
FCK : 256 FS CLOCK
FLTA : RECORDING FRAME SIGNAL
FLTT : TRANSFER/PLAYBACK FRAME SIGNAL
JDAT : INTERFACE
JRDY : INTERFACE
LRCI : FS SIGNAL
MDPL : (FOR TEST)
MUT
: DIRECT MUTING
NOIN : D/A THROUGH MODE AUDIO DATA
PS
: POWER SAVE MODE
RST
: RESET
SCK
: MICROCOMPUTER TRANSFER CLOCK
SFP1, SFP2 : PLAYBACK DATA
46
REF
SPSO : MICROCOMPUTER COMMUNICATION DATA
47
VAR
STR1, STR2 : REC/PB DATA COMMUNICATION START PULSE
48
INT
TCK : (FOR TEST)
53
TDI : (FOR TEST)
TRCK
54
TENA1, TENA3 : (FOR TEST)
FLTT
55
TRCK : MAIN CLOCK
FLTA
64
RESET
TRST : (FOR TEST)
TSAD : (FOR TEST)
59
STR1
61 TSRM : (FOR TEST)
STR2
TSTM : (FOR TEST)
60
SFP1
62 VST : (FOR TEST)
SFP2
57
OTEN
OUTPUT
58
SFDR
ATC
: AUTO ATT INTERFACE CLOCK
ATLT : AUTO ATT INTERFACE LATCH PULSE
65
PS
BCKO : 64 FS SIGNAL
74
DSP
DATO : AUDIO DATA (MSB FIRST FORMAT)
16
DSPO
DIIN : MICROCOMPUTER INTERFACE SERIAL/PARALLE CONVERSION
75
ATT
DSPO : ADSP INTERFACE CLOCK
18
ATLT
DV32 : INTERFACE
17
ATC
EMPA : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
ERRF : PB AUDIO DATA ERROR RECOGNITION SIGNAL
ERS
: RESET
FSE1, FSE2 : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
HEN
: INTERFACE
INT
: PLAYBACK PHASE CHECKING
LRCO : FS SIGNAL
LSBO : AUDIO DATA (LSB FIRST FORMAT)
OTEN : RECORDING DATA COMMUNICATION ENABLE
PBON : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
PCEZ : INTERFACE
PRST : INTERFACE
REF
: PHASE COMPARATOR REFERENCE CLOCK
SFDR : RECORDING DATA
SLVX : INTERFACE
SLXM : INTERFACE
SPSI : MICROCOMPUTER COMMUNICATION DATA
TDO : (FOR TEST)
VAR
: PHASE COMPARATOR COMPARISON CLOCK
VEN : INTERFACE
INPUT/OUTPUT
A0 - A14 : (FOR TEST)
CE
: (FOR TEST)
D0 - D7 : (FOR TEST)
OE
: (FOR TEST)
TDAT : (FOR TEST)
TSCK : (FOR TEST)
TSG
: (FOR TEST)
WE
: (FOR TEST)
PIN PIN PIN
I/O SIGNAL I/O SIGNAL
NO. NO.
26 — V 51 — V 76
DD DD
27 — GND 52 — GND 77
28 I FCK 53 I TRCK 78
29 I/O D3 54 I FLTT 79
30 I/O D2 55 I FLTA 80
31 I/O D1 56 I/O A14 81
32 I/O D0 57 O OTEN 82
OE
33 I/O 58 O SFDR 83
ERS
34 O 59 I STR1 84
35 O PRST 60 I SFP1 85
36 O PCEZ 61 I STR2 86
37 O VEN 62 I SFP2 87
38 — GND 63 — GND 88
HEN RST
39 O 64 I 89
PS
40 O SLXM 65 I 90
41 O SLVX 66 I/O A13 91
42 O DV32 67 I/O A12 92
WE
43 I/O 68 I/O A11 93
CE
44 I/O 69 I/O A10 94
SCK
45 I MDPL 70 I 95
REF
46 O 71 I SPSO 96
VAR
47 O 72 O SPSI 97
INT MUT
48 O 73 I 98
DSP
49 I JRDY 74 I 99
ATT
50 I JDAT 75 I 100
I/O SIGNAL
— V
DD
ACF
I
ACT
I
O PBON
O DIIN
I/O A9
I/O A8
I/O TSCK
TSG
I/O
I/O TDAT
I TSTM
I TSAD
— GND
I TSRM
I/O A7
I/O A6
I/O A5
I/O A4
I/O A3
I/O A2
I/O A1
I/O A0
O FSE2
O FSE1
O EMPA
DSR-1500/1500P