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Alto
Hardw~re
Manual
Section 4: Display Controller
32
4.0 DISPLAY CONTROLLER
4.1 Programming
Charactelistics
The display controller handles transfers between the main memory and the CRT. The CRT is a standard
875 line raster-scanned TV monitor, refreshed at 60 fields per second from a bit map in main memory.
The CRT contains 606 points horizontally, and 808 points vertically, or 489,648 points total.
The basic way in which information is presented on the display is by fetching a series of words from Alto
main memory, and serially extracting bits to become the video signal. Therefore, 38 16-bit words are
required to represent each scan line; 30704 words are required to
fill
the screen.
The display is defined by one or more display control blocks in main memory. Control blocks (DCB'S)
are linked together starting at location DASTART(420B) in page 1:
DASTART:
DASTART+1:
Pointer to word 0 of the first (top on the screen) DCB, or 0 if display is off.
Vertical field interrupt bit mask.
Every 1/60 second, this word is OR'ed into
NWW
to cause interrupts, even if the display is off (Le., rv(DASTART)
=
0).
Display control blocks must begin at even addresses in memory, and have the following format:
DCB:
Pointer to next DCB, or 0 if this is the last
DCB+l:
Bit 0:
0
=
high resolution mode
1
=
low resolution mode
Bit 1:
0
=
black on white background presentation
1
=
white on black background
Bits 2-7
(HTAB): On each scan line of this block, wait 16*HTAB bits before
displaying information from memory.
Bits 8-15
(NWRDS): Each scan line in this block is defined by NWRDS 16 bit
words.
(NWRDS must be even).
In order to skip space on the
screen without requiring bit-map, set NWRDS to O.
DCB+2 (SA):
Bit map starting address, which must be even.
DCB+ 3 (SLC): This block defmes 2*SLC scan lines, SLC in each field.
At the start of each field, the display controller inspects DASTART and DASTART+ 1.
An interrupt is
initiated on the channel(s) specified by the bites) in DASTART+
1.
The controller then executes each DCB
sequentially until the display list or the field ends. At normal resolution, the first scan line of the first
(even) field of a block is taken from location SA to SA + NWRDS-l, the first scan line of the odd field is
taken from locations SA + NWRDS to SA + 2*NWRDS-1. During each display field, the bit map address is
incremented by an extra NWRDS between each pair of scan lines. In low resolution mode, the video is
generated at half speed, and each scan line is displayed twice (once in each field). During each field, the
bit map address is not incremented by an extra NWRDS between the display of adjacent scan lines. This
makes the format of the bit map in memory identical for both modes--only the size of the presentation is
affected by the mode.
4.1 Hardware
The display controller consists of a sync generator, a data buffer and serializing shift register, and three
microcode tasks which control data handling and communicate with the Alto program. The hardware is
shown in block form in Figure 5. The 16 word buffer is loaded from the Alto bus with the DDR+-
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