Bootstrapping - Xerox Alto I Hardware Manual

Alto Hardware Manual Section 3: Emulator 29
STA 1 @ACTIVE
IMPLEMENTATION
In addition to the main memory locations, the interrupt system uses one R-register: NWW, new interrupts
waiting. Bit 0 of NWW is 0 if the interrupt system is enabled and one if it is disabled. This is why there
are only 15 channels of interrupts and why ww[O] should never be set.
lIO
device microcode ORS bits
into this register to cause interrupts.
(NWW
OR
WW)
expresses all pending interrupts.
The main loop of the emulator checks NWW during the fetch of each emulated instruction. If
hTWW
is
greater than zero (i.e., NWW[O] is not set meaning the interrupt system is on, and at least one bit is set in
NWW[I-IS] meaning an interrupt is pending on some channel) then the microcode computes (NWW OR
ww) AND ACTIVE. If this quantity is nonzero (Le., an interrupt is pending and its channel is active) then
an interrupt is caused. If not, NWW OR WW is stored in WW, NWW is zeroed, and the instruction is
restarted.
If an interrupt is caused, the microcode stores the program counter in PCLOC, sets NWW[O] to disable
further interrupts, clears the bit in NWW and in WW corresponding to the channel on which the interrupt
is occurring, and loads PC with rv(INTVEC+ IS-CHANNEL).
When the interrupt system is disabled (by executing DIR or DIRS or initiation of an interrupt), the
microcode sets NWW[O]. When the interrupt system is enabled (by executing EIR or BRI), the microcode
clears NWW[O] and ORS WW into
NWW.
This organization is optimized to minimize the cost (in additional microinstructions in the emulator main
loop) of the most common case where the interrupt system is enabled and no interrupts are pending.
When a . bit appears in
hTWW
while the interrupt system is· active, it is either cleared by causing an
interrupt or flushed into WW where it is checked less often, since the cost of deciding that an interrupt is
pending but that the channel is inactive is too high to tolerate on each pass through the main loop. The
assumption in flushing inactive bits into WW is that the CPU program will enable interrupts shortly after
changing· ACTIVE, and doing so will cause the pending bits in WW to be reconsidered.
3.3 Bootstrapping
The emulator contains microcode for initializing the Alto in certain ways, and thereby "bootstrapping" a
runnable program into the machine. A "boot," which is invoked either by pressing the small button at
the rear of the keyboard or by executing an appropriate 8IO instruction (see section 3.3), simply resets all
micro-PC's to fixed initial values determined by their task numbers. Unless the Reset Mode Register
specifies otherwise (see section 8.4), the emulator task is started in the PROM and performs a number of
operations:
1. The current value of PC is stored in memory location O. The emulator accumulators are not
·altered during booting.
2. The display is turned off; Le. rv(420B) +-0.
3. Interrupts are disabled.
4. The first keyboard word (KBDAD, 177034B) is read to determine what sort of boot is to be
done: .
Disk Boot: If the (BS) key is not depressed, the microcode interprets any depressed keys
reported in this keyboard word as a real disk address. If no keys are depressed,
this results in a real disk address . of O.