Configuration; Power Management; Document Revision History For Max 10 Fpga Device Overview - Intel MAX 10 FPGA User Manual

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1 MAX 10 FPGA Device Overview

1.15 Configuration

Table 12. Configuration Features
Feature
Dual configuration
Design security
SEU Mitigation
Dual-purpose configuration
pin
Configuration data
compression
Instant-on
Table 13. Configuration Schemes for MAX 10 Devices
Configuration Scheme
Internal Configuration
JTAG

1.16 Power Management

Table 14. Power Options
Power Options
Single-supply device
Dual-supply device
Power management
controller scheme

1.17 Document Revision History for MAX 10 FPGA Device Overview

Date
February 2017
December 2016
• Stores two configuration images in the configuration flash memory (CFM)
•
Selects the first configuration image to load using the
• Supports 128-bit key with non-volatile key programming
• Limits access of the JTAG instruction during power-up in the JTAG secure mode
• Unique device ID for each MAX 10 device
• Auto-detects cyclic redundancy check (CRC) errors during configuration
• Provides optional CRC error detection and identification in user mode
• Functions as configuration pins prior to user mode
• Provides options to be used as configuration pin or user I/O pin in user mode
• Decompresses the compressed configuration bitstream data in real-time during
configuration
• Reduces the size of configuration image stored in the CFM
Provides the fastest power-up mode for MAX 10 devices.
Compression
Yes
—
Saves board space and costs.
• Consumes less power
• Offers higher performance
• Reduces dynamic power consumption when certain applications are in standby mode
• Provides a fast wake-up time of less than 1 ms.
Version
2017.02.21 • Rebranded as Intel.
2016.12.20 • Updated EMIF information in the Summary of Features for MAX 10
Devices table. EMIF is only supported in selected MAX 10 device density
and package combinations, and for 600 Mbps performance, –6 device
speed grade is required.
• Updated the device ordering information to include P for leaded
package.
Description
CONFIG_SEL
Encryption Dual Image
Configuration
Yes Yes
— —
Advantage
Changes
pin
Data Width
—
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MAX 10 FPGA Device Overview
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