Questionable Status Register Set - Agilent Technologies 8712ET Programmer's Manual

Questionable Status Register Set

The Questionable Status register set monitors conditions that affect the
quality of measurement data.
Bits in the Questionable Status condition register are set to 1 under the
following conditions:
Limit Fail
(bit 9) is set to 1 when one or more enabled bits in the Limit
Fail event register are set to 1.
Data Questionable
(bit 10) is set to 1 when a change in the analyzer's
configuration requires that new measurement data be
taken.
Programmer's Guide
Using Status Registers
The Analyzer's Status Register Sets
5-19