Table of Contents
Advertisement
3. TECHNICAL BRIEF
Write Operation
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are deserted.
All device write operations are asynchronous, with CLK being ignored. During a write operation, address
and data are latched on the rising edge of WE # or CE#, whichever occurs first.
Output Disable
When OE# is deserted, device outputs D[15:0] are disabled and placed in a high-Impedance (High-Z)
state.
Standby Operation
When CE# is deserted the device is deselected and placed in standby, substantially Reducing power
consumption. In standby, the data outputs are placed in High-Z, independent of the level placed on OE#.
Standby current, ICCS, is the average current measured over any 5 ms time interval, 5 µs after CE# is
deserted. During standby, average current is measured over the same time interval 5 µs after CE# is
deserted.
When the device is deselected (while CE# is deserted) during a program or erase operation, it continues
to consume active power until the program or erase operation is completed.
Reset Operation
As with any automated device, it is important to assert RST# when the system is reset. When the system
comes out of reset, the system processor attempts to read from the flash memory if it is the system boot
device. If a CPU reset occurs with no flash memory reset, improper CPU initialization may occur
because the flash memory may be providing status information rather than array data.
Intel® flash memories allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array, and the Status Register
is set to 0x80. Asserting RST# de-energizes all internal circuits, and places the output drivers in High-Z.
When RST# is asserted, the device shuts down the operation in progress, a process which takes a
minimum amount of time to complete.
When RST# has been deserted, the device is reset to asynchronous Read Array state.
- 65 -
Advertisement
Table of Contents
