Table of Contents
Advertisement
3. TECHNICAL BRIEF
• FR71E Core
- Fujitsu FR series 32-bit RISC core for compatible instruction equipped, 5-level pipelines and
execution rate of 1 instruction/1 cycle
- 4 KBytes instruction cache and 8 KBytes data RAM equipped
- 24-bit address bus, 16-bit data bus
- Capable of directly accessing the external flash memory, SDRAM and SRAM
- Built-in peripheral functions: DMAC(5 ch), UART(2 ch), 16-bit reload timer(3 ch) and interrupt
controller
• DSP Core
- Using Fujitsu"s original 16-bit fixed-point DSP developed for audio processing
- Data RAM of two-sided structure which allows simultaneous access to both sides, ARAM and
BRAM (4kword each)
- Instruction memory comprising RAM(PRAM) of 16kword and can be freely rewritten at resetting
- DMA transfer between the external RAM domain and SDRAM possible
- Multiple-accumulate instruction: 40bits ± 16bits x 16bits > 40bits... with a guard bit of 8bits
• Image Processing
- CCD supporting RGB primary color bayer array, progressive interlace and 3/4/5/6 field
- Supporting VGA motion CCD by Sony and Matsushita
- Supporting REC656 input
- Supporting CCD of up to 16 million pixels
- Installed with the upgraded version of M3 algorithm
- Shading correction function equipped
- Custom Image Processor (4x matrix, gamma correction) equipped
- JPEG macro equipped (compression extension by JPEG Baseline method; calculation accuracy
following ISO/IEC10918-2
• SDRAMC
- Supporting DDR-SDRAM(x16) and SDR-SDRAM(x16/32)
However, when VGA motion is processed, x32 must be used for SDR-SDRAM
- Equipped with 2KByte data cache which can freely perform mapping in SDRAM area
- The DDR-SDRAM interface of this LSI uses the interface format of general DDRSDRAM.
- The DDR-SDRAM does not operate in Vtt termination mode (SSTL-II). The interface is without
termination.
- 54 -
Advertisement
Table of Contents
