Sony HBD-E2100 Service Manual page 72

HBD-E2100/E3100/E3200/E4100/E6100
Ver. 1.5
Pin No. Pin Name
K3 CAS
K4 NO_USE
K5 NO_USE
K6 NO_USE
K7 CK
K8 VDD
K9 CKE
L1 NC
L2 CS
L3 WE
L4 NO_USE
L5 NO_USE
L6 NO_USE
L7 A10
L8 ZQ
L9 NC
M1 VSS
M2 BA0
M3 BA2
M4 NO_USE
M5 NO_USE
M6 NO_USE
M7 NC
M8 VREFCA
M9 VSS
N1 VDD
N2 A3
N3 A0
N4 NO_USE
N5 NO_USE
N6 NO_USE
N7 A12
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I/O
I Command Input: CAS (along with CS) defi ne the command being entered.
- Not used
- Not used
- Not used
Clock: CK is differential clock input. All address and control input signals are sampled on the
I
crossing of the negative edge of CK. Output (read) data is referenced to the crossing of CK.
- Power Supply: 1.5V +/-0.075
Clock Enable: CKE HIGH activates, and CKE LOW deactivates, internal clock signal and de-
vice input buffers and output drivers. Talking CKE LOW provides Precharge Power-Down and
Self Refresh operation (all banks idle), or Active Power-Down (Row Active in any bank). CKE
is asynchronous for self refresh exit. After V
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initialization sequence, it must be maintained during all operations (including Self-Refresh).
CKE must be maintained high throughout read and write accesses. Input buffers, excluding
CK, CK, ODT and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during Self-Refresh.
- No Connect: No internal electrical connection is present.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external
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Rank selection on system with multiple Ranks. CS is considered part of the command code.
I Command Input: WE (along with CS) defi ne the command being entered.
- Not used
- Not used
- Not used
Address inputs: Provided the row address for active commands and the column address for
Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Autoprecharge: A10 is sampled during Read/Write commands to determine whether Auto-
I precharge should be performed to the accessed bank after the Read/Write operation. (HIGH:
Autoprecharge; LOW: No Autoprecharge)
A10 is sampled during a Precharge command to determine the Percharge applies to one bank
(A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by bank adresses.
- Reference Pin for ZQ calibration
- No Connect: No internal electrical connection is present.
- Ground
Bank Address Inputs: BA0 defi ne to which bank an Active, Read, Write or Precharge com-
I mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
Bank Address Inputs: BA2 defi ne to which bank an Active, Read, Write or Precharge com-
I mand is being applied. Bank address also determines if the mode register or extended mode
register is to be accessed during a MRS cycle.
- Not used
- Not used
- Not used
- No Connect: No internal electrical connection is present.
- Reference voltage for CA
- Ground
- Power Supply: 1.5V +/-0.075
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
Address inputs: Provided the row address for active commands and the column address for
I Read/Write commands to select one location out of the memory array in the respective bank.
The address inputs also provide the op-code during Mode Register Set commands.
- Not used
- Not used
- Not used
Address inputs: Provided the row address for active commands and the column address
for Read/Write commands to select one location out of the memory array in the respective
I bank. The address inputs also provide the op-code during Mode Register Set commands.
Burst Chop: A12 is sampled during Read and Write commands to determine if burst chop (on-
the-fl y) will be performed. (HIGH: no burst chop, LOW: burst chopped).
Description
has become stable during the power on and
REFCA