Only For Training And Service Purposes - LG GM310 Service Manual

Shared Memory Block
1.5K x 32bit Shared RAM(dual ported) between controller system and TEAKLite.
Controller Bus system
The processor cores and their peripherals are connected by powerful buses.
-Multi-layer AHB for connecting the ARM and the other master capable building blocks with the
internal and external memories and with the peripheral buses.
-An FPI-Bus for connecting GSM peripherals, called hereafter FPI3 bus.
-A controller FPI bus for connecting the low performance controller peripherals such as keypad,,
Called hereafter fPI2 bus.
-FPI2 and FPI3 are connected asynchronously to the AHB buses.
Clock system
The clock system allows widely independent selection of frequencies for the essential parts of the S-
GOLD3H-LC. Thus power consumption and performance can be optimized for each application.
Functional Hardware block
- CPU and DSP Timers
- MOVE coprocessor performing motion estimation for video encoding algorithms
(H.263, MPEG-4)
- Programmable PLL with additional phase shifters for system clock generation
- GSM Timer Module that off-loads the CPU from radio channel timing
- GMSK / 8-PSK Modulator according to GSM-standard 05.04 (5/2000)
- GMSK Modulator: gauss-filter with B*T=0.3
- EDGE Modulator: 8PSK-modulation with linearized GMSK-Pulse-Filter
- Hardware accelerators for equalizer and channel decoding.
- Incremental Redundancy memory for EDGE class 12 support
- A5/1, A5/2, A5/3 Cipher unit
- GEA1, GEA2, GEA3 Cipher Unit to support GPRS data transmission
- Advanced static and dynamic power management features including TDMA-Frame
synchronous low power mode and enhanced CPU modes(idle and sleep modes)
Copyright © 2009 LG Electronics. Inc. All right reserved.

Only for training and service purposes

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GM310f service manual
- 17 - LGE Internal Use Only