Samsung R60 NP-R60FY series Service Manual page 39

4 4
SAMSUNG PROPRIETARY SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY. SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG. EXCEPT AS AUTHORIZED BY SAMSUNG.
Put the AVDD,AVDDI,AVDDQ,PLVDD
D D
decoupling CAPS on the bottom side close to BALLS
P1.8V
BLM18PG181SN1
P1.2V
B14
C C
BLM18PG181SN1
P1.8V
R79 4.7K
VGA3_VSYNC
26-B3
VGA3_HSYNC
26-A3
R111 4.7K
CRT3_RED
26-D4
CRT3_GREEN
26-D4
CRT3_BLUE
26-C4
CLK3_NB14M
R90 R89 R88
CLK0_HCLK1
B B
CLK0_HCLK1#
150 150
150
1% 1%
1%
A A
4 4
3 3
P3.3V_NB
B508
BLM18PG181SN1 C599 U506-4
RS600ME
2200nF
10V 4 OF 5
A18
VDDR3_1
B18
VDDR3_2
C600
C598
4700nF
2200nF A17
6.3V AVDD_1
10V
B17
AVDD_2
nostuff
AVDDQ
M23
B16
AVSSN_1
N23
AVSSN_2
C80
A23
2200nF
AVDDQ
10V
P1.8V
A24
AVSSQ
B19
AVDDDI
CLOSE TO CRT CONN
C84
2200nF
10V A19
AVSSDI
M10
VDDPLL_PCIE_1
P13
VDDPLL_PCIE_2
P12
VDDPLL_PCIE_3
C74
C86
4700nF
2200nF V12
6.3V VSSPLL_PCIE_1
PLLVDD18
10V
T12
VSSPLL_PCIE_2
T13
nostuff
VSSPLL_PCIE_3
B13
A14
PLLVDD18
A12
PLLVDD12
C72 C73
BLM18PG181SN1
2200nF 2200nF
10V 10V
A11
PLLVSS
P3.3V_NB
P3.3V_NB
B26
TMDS_HPD
4.7K R84
B12
DDC_DATA
B23
DACVSYNC
B24
DACHSYNC
R87 681
A25
DAC_RSET
1%
D19
RED
F19
GREEN
J19
BLUE
B11
OSCIN
7-B1 A7
CPU_CLKP
B7
7-C1
CPU_CLKN
7-C1
P1.8V P5.0V_ALW P3.3V
R573
R571
R579 R570
30K 10K
SI2315BDS-T1
3
1 Q515
MMBT3904
C597
470nF 2
16V
P3.3V_NB CONTROL CIRCUIT
3 3
C24
TXOUTU0N_RESERVED
C25
TXOUTU0P_RESERVED
D24
TXOUTU1N_RESERVED
E24
TXOUTU1P_RESERVED
H21
TXOUTU2N_RESERVED
J21
TXOUTU2P_RESERVED
E23
TXOUTU3N_RESERVED
F23
TXOUTU3P_RESERVED
B28
TXOUTL0N_RESERVED
A28
TXOUTL0P_RESERVED
C30
TXOUTL1N_RESERVED
B30
TXOUTL1P_RESERVED
B29
TXOUTL2N_RESERVED
A29
TXOUTL2P_RESERVED
C28
TXOUTL3N_RESERVED
C27
TXOUTL3P_RESERVED
E21
TXCLKUN_RESERVED
F21
TXCLKUP_RESERVED
A27
TXCLKLN_RESERVED
B27
TXCLKLP_RESERVED
J23
VDDLT33_1
H23
VDDLT33_2
H24
VDDLT18_1
J24
VDDLT18_2
A30
VSSLT_1
A26
VSSLT_2
C29
VSSLT_3
F24
VSSLT_4
B21
LTPVDD18
A21
LTPVSS18
D3
GPIO3_LVDSDIGON
C4
GPIO2_LVDSBLON
C5
GPIO4_LVDSENABL
J18
C_PR
F18
Y
D18
COMP_PB
A22
DAC_SDA
C21
SMB_CLK
B22
SMB_DATA
B14
STRAP_DATA
P3.3V_NB P1.8V
0
0
3
2 1
R572
Q517
BAV99LT1
D512
33
nostuff
nostuff
3
D
nostuff
nostuff
Q516
nostuff
RHU002N06
G nostuff
nostuff
1
nostuff
S 2
nostuff
2 2
LCD1_ADATA0#
25-C4
LCD1_ADATA0
25-C4
LCD1_ADATA1#
25-C3
LCD1_ADATA1
25-C3
LCD1_ADATA2#
25-C4
LCD1_ADATA2
25-C4
LCD1_ACLK#
25-C3
LCD1_ACLK
25-C3
C78 C76
100nF 4700nF
10V 6.3V
nostuff
C117 C115
100nF 4700nF
10V 6.3V
nostuff
C83
C82
100nF
2200nF
10V
10V
LCD3_VDDEN
P3.3V_NB
25-D2 25-B4
LCD3_BKLTCTRL
25-D4
LCD3_BKLTEN
25-B4
R83 0
R80
0
STRAP DEFINITIONS FOR THE RS600M
STRAP PIN DESCRIPTION
DACHSYNC Enable/Disable integrated graphics.
0 : Enable integrated graphics
1 : Disable integrated graphics
STRP_DATA Debug strap configuration. This strap should not be set to "0" on production boards.
0 : Select Memory Channel A to be a debug bus
1 : Read debug straps from an external EEPROM, or disable debug mode when an EEPROM is absent.
DACVSYNC Select configuration of the integrated graphics engine.
0 : Reserved
1 : Required setting for the RS600M
DDC_DATA Select DDR2 or DDR3 signalling level for the memory interface.
0 : DDR3. On DDR3, it is necessary to put an isolation FET in series with the pull-up
resistor on this strap to separate it from the I2C circuit during an NB reset
1 : DDR2
2 2
1 1
P3.3V_NB
B15
C77 BLM18PG181SN1
2200nF
10V
P1.8V
B21
BLM18PG181SN1
C116
2200nF
10V
CRT3_DDCDATA
26-B2
LCD3_EDID_CLK
25-C4
CRT3_DDCCLK
26-A2
LCD3_EDID_DATA
25-C4
C81 C79
0.1nF 0.1nF
SAMSUNG
ELECTRONICS
1 1
D D
C C
B B
A A