Sony DSR-1800 Service Manual page 17

INPUT
ACF
: MICROCOMPUTER FRAME COMMUNICATION CHIP SELECT
ACT
: MICROCOMPUTER TRACK-PAIR COMMUNICATION CHIP SELECT
ATT
: AUTO ATT INTERFACE CHIP SELECT
BCKI : 64 FS SIGNAL
DATI : AUDIO DATA
DSP
: ADSP INTERFACE CHIP SELECT
FCK : 256 FS CLOCK
FLTA : RECORDING FRAME SIGNAL
FLTT : TRANSFER/PLAYBACK FRAME SIGNAL
JDAT : INTERFACE
JRDY : INTERFACE
LRCI : FS SIGNAL
MDPL : (FOR TEST)
MUT
: DIRECT MUTING
NOIN : D/A THROUGH MODE AUDIO DATA
PS
: POWER SAVE MODE
RST
: RESET
SCK
: MICROCOMPUTER TRANSFER CLOCK
SFP1, SFP2 : PLAYBACK DATA
SPSO : MICROCOMPUTER COMMUNICATION DATA
STR1, STR2 : REC/PB DATA COMMUNICATION START PULSE
TCK : (FOR TEST)
TDI : (FOR TEST)
TENA1, TENA3 : (FOR TEST)
TRCK : MAIN CLOCK
TRST : (FOR TEST)
TSAD : (FOR TEST)
TSRM : (FOR TEST)
TSTM : (FOR TEST)
VST : (FOR TEST)
OUTPUT
ATC
: AUTO ATT INTERFACE CLOCK
ATLT : AUTO ATT INTERFACE LATCH PULSE
BCKO : 64 FS SIGNAL
DATO : AUDIO DATA (MSB FIRST FORMAT)
DIIN : MICROCOMPUTER INTERFACE SERIAL/PARALLE CONVERSION
DSPO : ADSP INTERFACE CLOCK
DV32 : INTERFACE
EMPA : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
ERRF : PB AUDIO DATA ERROR RECOGNITION SIGNAL
ERS
: RESET
FSE1, FSE2 : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
HEN
: INTERFACE
INT
: PLAYBACK PHASE CHECKING
LRCO : FS SIGNAL
LSBO : AUDIO DATA (LSB FIRST FORMAT)
OTEN : RECORDING DATA COMMUNICATION ENABLE
PBON : MICROCOMPUTER INTERFACE SERIAL/PARALLEL CONVERSION
PCEZ : INTERFACE
PRST : INTERFACE
REF
: PHASE COMPARATOR REFERENCE CLOCK
SFDR : RECORDING DATA
SLVX : INTERFACE
SLXM : INTERFACE
SPSI : MICROCOMPUTER COMMUNICATION DATA
TDO : (FOR TEST)
VAR
: PHASE COMPARATOR COMPARISON CLOCK
VEN : INTERFACE
INPUT/OUTPUT
A0 - A14 : (FOR TEST)
CE
: (FOR TEST)
D0 - D7 : (FOR TEST)
OE
: (FOR TEST)
TDAT : (FOR TEST)
TSCK : (FOR TEST)
TSG
: (FOR TEST)
WE
: (FOR TEST)
73
MUT
6
ERRF
15 A/D, D/A
NOIN
INTERFACE
14
DATI
BLOCK
12
DATO
11
LSBO
SELF-CHECK
BLOCK
RAM
RAM
INTERFACE
BLOCK
49
JRDY
50
JDAT
DSR-1800/P/1600/P
PEAK LEVEL METER BLOCK
MUTING
MULT BUS
BLOCK
REC PB
BLOCK BLOCK
ADDRESS BUS
CXD3104R
INTERFACE
BLOCK
DATA BUS
CXD2912
CXD2913 MICROCOMPUTER
INTERFACE INTERFACE BLOCK
BLOCK
BA6247FP-YE2 (ROHM)
REVERSIBLE MOTOR DRIVER
—TOP VIEW—
OUT3 1 25 NC 5P IN1
0
NC NC
2 24
1
NC NC
3 23
1
NC 4 22 OUT2
0
IN1 5 21 NC
0
IN2 6 20 GND
1
0 : LOW LEVEL
1 : HIGH LEVEL
GND 7
IN3 8 19 GND
V 9 18 OUT1
CC1
NC 10 17 NC
NC V
11 16 CC2
NC NC
12 15
NC 13 14 VR
18 22
OUT1 OUT2
5
IN1 CONTROL CIRCUIT
6
IN2
8
9
IN3
V 1
CC
46
REF
47
VAR
48
INT
53
TRCK
54
FLTT
55
FLTA
64
RESET
59
STR1
61
STR2
60
SFP1
62
SFP2
57
OTEN
58
SFDR
65
PS
74
DSP
16
DSPO
75
ATT
18
ATLT
17
ATC
INPUTS OUTPUTS
FUNCTION
6P IN2 8P IN3 18P OUT1 22P OUT2 1P OUT3
0
0 0 0 0 BRAKE
1
CURRENT
0 0 1 0 OPEN
OUT1 TO OUT2
CURRENT
0 1 0 1 OPEN
OUT2 TO OUT1
CURRENT
1 0 1 OPEN 0
OUT1 TO OUT3
CURRENT
1 1 0 OPEN 1
OUT3 TO OUT2
0
1 0 0 0 BRAKE
1
16
V 2
CC
V
R
14
1
OUT3
GND
THERMAL
SHUTDOWN
CIRCUIT
11-7
IC