Processor 2/7 - Clevo P170HM Service Manual

Schematic Diagrams

Processor 2/7

Add to connect to EC
Sheet 3 of 58
Processor 2/7
Buffered reset to CPU
14,23,58 PLT_RST#
R511
100K_04
B - 4 Processor 2/7
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
PROC_SELET
24 PROC_SELET
H_CATERR#
R50 *10mil_short
24,34 H_PECI
R52 56_04 H_PROCHOT#_D
43 H_PROCHOT#
R51 *10mil_short
24 H_THRMTRIP#
R302 *10mil_short
21 H_PM_SYNC
R41 *10mil_short H_CPUPWRGD_R
24 H_CPUPWRGD
VDDPWRGOOD_R
3.3VS
1.05VS_VTT
BUF_CPU_RST#
R97
R39
10K_04 75_04
Q38
G
R40 43.2_1%_04 BUF_CPU_RST#
MTN7002ZHS3
Q37
R38 *1.5K_1%_04
G
34 H_PROCHOT#_EC
C60 MTN7002ZHS3 R48
68P_50V_04
*750_1%_04
3.3V 3.3V
PM_DRAM_PWRGD
R107 R118
*10K_04
PM_DRAM_PWRGD
*200_04
21 PM_DRAM_PWRGD
Q11
R115
G
*MTN7002ZHS3
*100K_04
39,41 +1.5S_CPU_PWRGD
Q8
R103
G
*MTN7002ZHS3
*100K_04
U32B
A28
BCLK
C26 A27
SNB_IVB# BCLK#
AN34
SKTOCC# A16
R322 1K_04
DPLL_REF_SSCLK A15
R325 1K_04
DPLL_REF_SSCLK#
AL33
CATERR#
AN33 R8 CPUDRAMRST#
PECI SM_DRAMRST#
AL32 AK1
SM_RCOMP_0
PROCHOT# SM_RCOMP[0]
A5
SM_RCOMP_1
SM_RCOMP[1]
A4 SM_RCOMP_2
SM_RCOMP[2]
AN32
THERMTRIP#
AP29
XDP_PRDY#
PRDY #
AP27
XDP_PREQ#
PREQ#
AR26 XDP_TCLK
TCK
AR27 XDP_TMS
TMS
AM34 AP30 XDP_TRST#
PM_SY NC TRST#
AR28
XDP_TDI_R
TDI AP26
XDP_TDO_R
TDO
AP33
UNCOREPWRGOOD
AL35 XDP_DBR_R
DBR#
V8
SM_DRAMPWROK
AT28
BPM#[0]
AR29
BPM#[1]
AR30
AR33 BPM#[2] AT30
RESET# BPM#[3]
AP32
BPM#[4]
AR31
BPM#[5]
AT31
BPM#[6]
AR32
BPM#[7]
PZ98927-3641-01F
H_PROCHOT#
Q6 C82 68P_50V_04
G
MTN7002ZHS3
R34
100K_04
1.5VS_CPU
R132
R117
0_04
200_04
R127 130_04
DRAMPWRGD_CPU VDDPWRGOOD_R
R128
Q10
G
*39_04
*MTN7002ZHS3
Q13
G
25,39,40,41,42 SUSB
*MTN7002ZHS3
PU/PD for JTAG signals
1.05VS_VTT
XDP_TMS
R82 51_04
XDP_TDI_R R76 51_04
XDP_PREQ# R84 *51_04
XDP_TDO_R R308 51_04
XDP_TCLK R309 51_04
XDP_TRST# R67 51_04
CLK_EXP_P 20
CLK_EXP_N 20
1.05VS_VTT
DDR3 Compensation Signals
SM_RCOMP_0 R409 140_1%_04
SM_RCOMP_1
R333 25.5_1%_04
SM_RCOMP_2 R334 200_1%_04
Processor Pullups/Pull downs
1.05VS_VTT
H_PROCHOT#
62_04 R42
H_CPUPWRGD_R
10K_1%_04 R49
C449 0.1u_16V_Y5V_04
D02A
TRACE WIDTH 10MIL, LENGTH <500MILS
3.3VS
XDP_DBR_R 1K_04 R301
S3 circuit:- DRAM_RST# to memory
1.5V
should be high during S3
R329
1K_04
R327 *0_04
BSS138 ( VGS 1.5V )
Q24
RJU003N03T106
S D
CPUDRAMRST#
R331
R328 1K_04
DDR3_DRAMRST# 10,11,12,13
4.99K_1%_04
DRAMRST_CNTRL 9,20
C494
*47n_50V_04
3.3VS 10,11,12,13,14,15,16,17,18,19,20,21,23,24,25,26,29,30,32,33,34,35,36,39,40,43,58
3.3V 3,9,14,15,19,20,21,23,24,25,26,28,29,30,32,35,36,37,39,40,41,42
1.5V 9,10,11,12,13,26,30,37,39,41
1.5VS_CPU 7,39
1.05VS_VTT 3,6,24,25,26,40,43