Icom IC-7800 Service Manual Addendum page 354

• DSP SYSTEM CLOCK CIRCUIT
The 40 MHz reference signal is applied to the amplifier
(IC652) via the "40M" line, and is then applied to the DDS IC
(IC651, pin 7) as the system clock signal. The signals which
are output from pins 14–22 are applied to the D/A convertor
(R661–R671, R673–R681), and then passes through the
low-pass (L681, L682, C680–C685) and high-pass (L683,
• RXPLL-A/B CIRCUITS
Reference oscillator
X1: 10 MHz
Q22
OSC unit
CAL
4 ATT
Q702
RXPLL-A unit
4 ATT
Q702
RXPLL-B unit
Q70
DDS IC
IC501 Q541
DDS IC
IC651
Q150
DDS IC
IC101
D/A
ATT
Q302
DDS IC
IC501 Q541
DDS IC
IC651
Q601
Q150
DDS IC
IC101
D/A
ATT
Q302
C686–C688) filters to suppress unwanted signals. The fil-
tered signal is amplified at the buffer amplifier (Q680), and
passes through the attenuator (R690–R692). The signal is
applied to the DSP IC for TX (DSP-TX board; IC1), RX-A
(DSP-A board; IC1) and RX-B (DSP-B board; IC1) as
12.288 MHz system clock signal via the A/D converters.
Q591
D821
ATT
Q680
PLL IC
IC201 *VCO
Q303
ATT
Q680
PLL IC
IC201 *VCO
Q303
3 - 10
64 MHz T2 LO signal
64.491 MHz R2 LO signal
Q831
0.491 MHz T3 LO signal
100 kHz Marker signal
*VCO is composed as below.
Q220: 64.485–72.454999 MHz
Q230: 72.455–79.454999 MHz
Q301
Q240: 79.455–86.454999 MHz
Q250: 86.455–94.454999 MHz
Q260: 94.455–109.454999 MHz
Q270: 109.455–109.455 MHz
R1 LO signal
T1 LO signal
64.591 MHz S2 LO signal
12.288 MHz DACK signal
140 MHz SAD signal
100 kHz Marker signal
*VCO is composed as below.
Q220: 64.585–72.554999 MHz
Q301
Q230: 72.555–79.554999 MHz
Q240: 79.555–86.554999 MHz
Q250: 86.555–94.554999 MHz
Q260: 94.555–109.554999 MHz
Q270: 109.555–109.555 MHz
S1 LO signal