Sony HCD-V5500 Service Manual page 27

Pin No. Pin Name I/O
45 TCK I
46 TDO O
47 VSS —
48 SI I
49 SCK I
50 XCS I
51 XVRST I
52 F1 I
53 VDD —
54 XTEST4 I
55 XRST I
I
56 SYSCLK
57 PDCLK O
58 VSS —
59 VSYNC O
60 HSYNC O
61 SO O
62 FID O
63 VDD —
64 XIICEN I
Test mode control input pin. Fix at "H"
Test data bus pin. (Not used)
Digital ground
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the SI serial data input pin.
When the XIICEN pin is "L", sets into the I
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the SCK serial clock input pin.
When the XIICEN pin is "L", sets into the I
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the XCK chip select input pin.
When the XIICEN pin is "L", sets into the I
signal which selects the I 2 C-BUS slave address
Active "L" vertical sync reset input pin. Pulled-up.
Used for synchronizing external vertical sync and internal vertical sync.
When XVRST is "L", the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined by this signal.
"H" indicates the first field.
"L" indicates the second field
Digital power supply
Test mode control input pin. Pulled-up.
When these pins are "H", CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active "L".
During power on/reset, set to "L" for more than 40 clocks (SYSCLK)
System clock input pin.
To generate the correct sub carrier frequency, precisely 27MHz is required
13.5MHz pixel data clock output pin. This clock is obtained by 1/2 frequency-dividing SYSCLK.
Used only in the 16-bit pixel data mode
Digital ground
V.sync signal output
H.sync signal output
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is "H", sets into the SONY SIO mode, and becomes the S0 serial-out output pin.
When the XIICEN pin is "L", this pin is not used and sets into high impedance (Not used)
Field ID output.
When control register bit "FDS"="1", "L" indicates the first field and "H" indicates the second field.
When control register bit "FDS"="0", "H" indicates the first field and "L" indicates the second field
Digital power supply
Serial interface mode selection input pin. Pulled-up.
When "L", Pins 48 to 50, and 61 set into the I
When "H", Pins 48 to 50, and 61 set into the SONY SOP mode
— 65 —
Description
2
C-BUS mode, and becomes the SDA input/output pin
2 C-BUS mode, and becomes the SCL input pin
2
C-BUS mode, and becomes the SA slave address selection input
2 C-BUS mode.