Schematic Diagram - Yamaha RX-V557 Service Manual

A B C
SCHEMATIC DIAGRAM (DSP 1/2)
1
3.4 4.9
3.4 4.9
2 0
BUFFER
0.1 3.4
4.9 0.1 3.4
4.9
0
0
3
4.0
0
4.9
4.3
4
0
4.9
4.0
0
4.9
BUFFER
4.9
2.3 1.8
4.4
5
DIGITAL IN
0.1 4.9 4.9
0.1
0 4.9 0
6
7
8
9
IC1: SN74LVU04APWR IC3: SN74AHCT00PWR
Hex Inverters Quad 2-Input Nand Gate
1
1A 14 VCC 1A 1 14 Vcc
1Y 2 13 6A 1B 2 13 4B
2A 3 12 6Y 1Y 3 12 4A
2A 4 11 4Y
2Y 4 11 5A
2B 5 10 3B
3A 5 10 5Y
2Y 6 9 3A
6
3Y 9 4A
GND 7 8 3Y
GND 7 8 4Y
10
D E F
3.4 3.4
0.1 3.4
3.4
0
4.0 0.1
4.3 0.1
0 DIR 0
3.4
3.4
4.0 1.6
4.4 1.6
A-3
0.1
1.7
3.4 3.4
0 0
3.4
0 0
0.1
1.3
0
3.4
3.4
3.4
0
1.3
0.1
1.3
0
0.1
0.1
1.7
1.3
0
1.7
MAIN
3.4
0
DECODER
1.3
0
3.1
3.0
3.4
0
1.3
0.5
0
1.3
3.4
3.4
1.3
3.4
0
1.3
3.4
0
0
1.3
1.3
0
IC11: µPC29M33T-E1
IC10: SN74LV245APWR
Octal Bus Transceiver with 3-state Outputs Voltage Regulator
1 INPUT
DIR 1 20 Vcc
Safety Drive
A1 2 19 OE Limiter
Amp.
A2 3 18 B1
3 OUTPUT
A3 4 17 B2
A4 5 16 B3
Excessive Electric
A5 6 15 B4 Current Protection
2 GND
A6 7 14 B5
A7 8 13 B6
A8 9 12 B7
GND 10 11 B8
G H I
Point: A-3 Pin 28 of IC2
0 3.4 0 3.4
1.7 0 3.4 0
1.7 0.1 1.7 0
0.1 0 0.1 0
1.7 0.1 3.4
1.9 1.7 0.1 0
1.8 0.2 3.4 0
0 1.7 0
SELECTOR
DIGITAL IN
ANALOG IN
3.4
1.7
0.2
1.7
1.3
0.1
1.3
1.3
0
~
1.3
1.3
0.1
0.1
0
3.4
1.7
1.7
3.4
DIGITAL IN
3.4
0
1.3
3.1
3.2
3.2
3.2
3.2
3.2
3.4
0
16M SRAM
1.3
3.2
3.2
3.2
3.2
3.2
3.2 3.5
3.2 3.1
1.3 3.2
0 0
3.4 3.2
3.1 3.2
3.2 3.5
3.2 3.4
3.4 3.2
0
3.2 3.2
3.4 3.2
0 3.5
1.3 3.2
3.4
3.4
3.4
3.4
0.8
0.2
0.4
0.4
0.4
3.4
3.5
DSP
IC12: SN74AHC1G08DCKR IC13: PQ012FZ01ZP IC22: SN74AHCT08PWR
2-Input And Gate Voltage Regulator Quad 2-Input And Gate
DC input DC output
1 3
A 1 5 Vcc 1A
(Vin) (Vo)
B 2 1B
Specific IC
1Y
GND 3 4 Y
Bias power supply ON/OFF control
2 4
(VB) (Vc)
2A
5
2B
GND
2Y
GND
J K L
RX-V557/HTR-5850/DSP-AX557/RX-V457/HTR-5840/DSP-AX457
RX-V557/DSP-AX557: Page 88 J9
HTR-5850: Page 89 J9
RX-V457/HTR-5840/DSP-AX457: Page 90 J9
to SUBTR (2)
IC2: LC89057W-VF4D-E
Digital Audio Interface Transceiver
RXOUT 1
RX0 2
RX1 3
RX2 4
RX3 5
RX4 8
RX5/VI 9
RX6/UI
10
LPF 13
TMCK/PIO0 44
TBCK/PIO1 45
TLRCK/PIO2 46
TDATA/PIO3 47
TXO/PIOEN 48
IC6: W9816G6CH
512K x 2 Banks x 16 Bits SDRAM
CLK 35
CLOCK
BUFFER
CKE 34
CS 18
RAS 17
COMMAND
CAS 16 DECODER
WE 15
A10 20
A0 21
∼
A3 24 ADDRESS
BUFFER
A4 27
∼
A9 32
BA 19
REFRESH
COUNTER
IC7: SN74LV157APWR
Quadruple 2-line to 1-line data selectors/multiplexers
1A 2
1B 3
2A
5
2B
6
3A 11
3B 10
4A
14
ANALOG IN
4B
13
G 15
A/B
1
4M ROM
IC8: MBM29LV400BC
0
FLASH MEMORY
3.2 0.2 0.2
3.1 0.2 3.5
0 0.2 0
0.2 3.2
3.2
3.2 0.8 3.2
V
CC
3.5 0.2 3.1
V SS
0.2 3.2
3.2
3.2 0.2 3.2
0 3.2
WE
3.2
3.2
3.2 3.4 3.2 BYTE
3.5 3.4 3.5
RESET
3.2
3.2 3.2
1.8 3.2
0.2
3.2
3.5
CE
0.2 3.2
OE
0.2 1.7 3.2
0.2 2.1 3.2
1.7 2.5 3.1
2.1 2.7
2.5 3.4 0
2.7 0.4 3.4
0 0.4 0.4
A 0 to A 17
A -1
IC26: SN74AHCT1G32DCKR
2-Input or Gate
1 14 Vcc A 1 5 Vcc
2 13 4B B 2
3 12 4A
GND 3 4 Y
4 11 4Y
5 10 3B
6 9 3A
# All voltages are measured with a 10MΩ/V DC electronic volt meter.
7 8 3Y
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
★ 電圧は、内部抵抗10MΩの電圧計で測定したものです。
★ s 印のある部品は、安全性確保部品を示しています。部品の交換が必要な場合、パーツリス
トに記載されている部品を使用してください。
★ 本回路図は標準回路図です。改良のため予告なく変更することがございます。
M N
EMPHA/UO AUDIO/VO INT CL CE CI XMODE
32 33 35 48 39 38 41
Microcontroller
Cbit, Ubit
37 DO
I/F
36 RERR
Demodulation
Input Data
& 21 RDATA
Selector Selector
Lock detect
24 SDIN
16 RMCK
PLL
17 RBCK
Clock 20 RLRCK
Selector
22 SBCK
Modulation
1/N
& 23 SLRCK
Parallel Port
29 28 27 34
XIN XOUT XMCK CKST
CONTROL COLUMN DECODER
SIGNAL R
GENERATOR O
W
D CELL ARRAY
E 2 DQ0
BANK #0
C
3 DQ1
O
D
E 5 DQ2
R
6 DQ3
SENSE AMPLIFIER
8 DQ4
9 DQ5
MODE
11 DQ6
REGISTER
12 DQ7
REFRESH DQ
COUNTER BUFFER 39 DQ8
40 DQ9
42 DQ10
43 DQ11
45 DQ12
46 DQ13
COLUMN COLUMN DECODER
48 DQ14
COUNTER
R
O 49 DQ15
W
D CELL ARRAY
E
BANK #1
C
O
D
E 14 LDQM
R
36 UDQM
SENSE AMPLIFIER
A/B V
1 16
CC
1A G
2 15
4 1Y
1B 4A
3 14
1Y 4B
4 13
2A 5 12 4Y
2B 6 11 3A
7 2Y
2Y 7 10 3B
GND 8 9 3Y
9 3Y
12 4Y
DQ to DQ
0 15
RY/BY
RY/BY
Buffer
Erase Voltage Input/Output
Generator Buffers
State
Control
Command
Register
Program Voltage
Chip Enable
Generator
STB Data Latch
Output Enable
Logic
Y-Decoder Y-Gating
STB
Timer for
Low V Detector Address
CC Program/Erase
Latch
X-Decoder Cell Matrix
A 15 1 48 A 16
A 14 2 47 BYTE
A 3 46 V
13 SS
A DQ /A
12 4 45 15 -1
A 11 5 44 DQ 7
A 6 43 DQ
10 14
A 7 DQ
9 42 6
A 8 8 41 DQ 13
N.C. 9 40 DQ
5
N.C. 10 DQ
39 12
WE 11 38 DQ 4
RESET 12 37 V CC
N.C. 13 36 DQ
11
N.C. DQ
14 35 3
RY/BY 15 34 DQ 10
N.C. 16 33 DQ
2
A 17 DQ
17 32 9
A 7 18 31 DQ 1
A 19 30 DQ
6 8
A 20 DQ
5 29 0
A 4 21 28 OE
A 3 22 27 V SS
A 23 26 CE
2
A A
1 24 25 0
81