Figure 3-5. Abacus Iii (Ad9874) Functional Block Diagram (From Data Sheet) - Motorola ASTRO XTS 5000 Detailed Service Manual

Theory of Operation: Transceiver Board
3.1.2.2 Receiver Back End
The receiver back end, which consists of the Abacus III (AD9874 IF digitizing subsystem) IC and its
associated circuitry, processes the down-converted IF signal to produce digital data for final
processing by the VOCON DSP.
NOTE: Refer to
listing of receiver back end schematics.
3.1.2.2.1 Abacus III IC U500
The AD9874 (Figure
IF input with a bandwidth up to 270 kHz. The output of the Abacus III IC is SSI data to the VOCON.
The signal chain of the AD9874 consists of a low-noise amplifier, a mixer, a bandpass sigma-delta
A/D converter, and a decimation filter with programmable decimation factor. An automatic gain
control (AGC) circuit provides the AD9874 with 12 dB of continuous gain adjustment. The high
dynamic range and inherent anti-aliasing provided by the bandpass sigma-delta converter allow the
AD9874 to cope with blocking signals 80 dB stronger than the desired signal.
Auxiliary blocks include frequency synthesizers for the second LO and sampling clock LO, as well as
an SPI port. The second LO uses a discrete external loop filter and VCO. The clock oscillator has an
external loop filter and resonator.
AD9874
-16dB
IFIN
LNA
FREF
LO
Synth.
LO VCO and
Loop Filter

Figure 3-5. Abacus III (AD9874) Functional Block Diagram (from data sheet)

VHF: Input signal RXIF is the 44.8 MHz IF from crystal filter FL451 in the receiver front end.
Components C547 and L542 match the input impedance from 50 ohms at the RXIF to the Abacus
input IFIN.
6881094C31-D
Table 8-1, "List of Transceiver Schematics and Board Overlays," on page 8-1
3-5) is a general-purpose, IF subsystem that digitizes a low-level 10–300 MHz
Samp. Clock
Synthesizer
CLK VCO and
Loop Filter
DAC AGC
Decimation
ADC
Filter
......=13-26MHz
Control Logic
Voltage/
Current
Reference
DOUTA
Formatting/SSI
DOUTB
FS
CLKOUT
SPI
MAEPF-27412-O
July 21, 2004
3-7
for a