interrupt can be routed to the same ISA IRQ line. The PIB can be
programmed to handle the PCI interrupts if the RavenMPIC is either not
present or not used.
The following figure shows the interrupt structure of the PIB.
PIRQ0_
PIRQ Route
Control Register
PIRQ1_
PIRQ Route
Control Register
PIRQ2_
PIRQ Route
Control Register
PIRQ3_
PIRQ Route
Control Register
Figure 5-2. PIB Interrupt Handler Block Diagram
http://www.motorola.com/computer/literature
Timer1/Counter0
IRQ1
IRQx
IRQ3
IRQ4
IRQ5
IRQ6
IRQx
IRQ7
IRQx
IRQ8
IRQ9
IRQ10
IRQ11
IRQx
IRQ12
IRQ13
IRQ14
IRQ15
Interrupt Handling
0
1
2
3
INTR
Controller 1
(INT1)
4
5
6
7
0
1
2
3
Controller 2
(INT2)
4
5
6
7
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