Page 1 MVME2300 Series VME Processor Module Programmer’s Reference Guide V2300A/PG5 Edition of June 2001...
Page 2 All rights reserved. Printed in the United States of America. ® Motorola and the Motorola logo are registered trademarks of Motorola, Inc. ® PowerPC is a registered trademark of International Business Machines Corporation and is used by Motorola with permission.
Page 3: Safety Summary
The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
Page 4: Lithium Battery Caution
All Motorola PWBs (printed wiring boards) are manufactured with a flammability rating of 94V-0 by UL-recognized manufacturers. This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to electromagnetic interference (EMI) if not installed and used with adequate EMI protection.
Page 5 While reasonable efforts have been made to assure the accuracy of this document, Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Page 6 If the documentation contained herein is supplied, directly or indirectly, to the U.S. Government, the following notice shall apply unless otherwise agreed to in writing by Motorola, Inc. Use, duplication, or disclosure by the Government is subject to restrictions as set forth in subparagraph (b)(3) of the Rights in Technical Data clause at DFARS 252.227-7013 (Nov.
Page 7: Table Of Contents
About This Manual Summary of Changes ... xx Overview of Contents ...xxi Comments and Suggestions ...xxi Conventions Used in This Manual...xxii CHAPTER 1 Board Description and Memory Maps Introduction...1-1 Overview...1-1 Summary of Features ...1-2 System Block Diagram ...1-3 Functional Description...1-6 VMEbus Interface...1-6 Front Panel...1-6 PCI interface ...1-7...
Page 8 CPU Control Register ... 1-30 ISA Local Resource Bus... 1-31 W83C553 PIB Registers ... 1-31 16550 UART ... 1-31 General-Purpose Readable Jumpers ... 1-32 NVRAM/RTC and Watchdog Timer Registers ... 1-32 Module Configuration and Status Registers... 1-33 CPU Configuration Register ... 1-34 Base Module Feature Register ...
Page 9 PCI Master ...2-17 Generating PCI Cycles ...2-21 Endian Conversion...2-25 When MPC Devices are Big-Endian ...2-25 When MPC Devices are Little-Endian ...2-27 Raven Registers and Endian Mode...2-27 Error Handling ...2-28 Transaction Ordering ...2-29 Raven Registers ...2-30 MPC Registers ...2-30 Vendor ID/Device ID Registers ...2-32 Revision ID Register ...2-33 General Control-Status/Feature Registers ...2-33 MPC Arbiter Control Register...2-36...
Page 10 Nesting of Interrupt Events ... 2-62 Spurious Vector Generation ... 2-62 Interprocessor Interrupts (IPI)... 2-62 8259 Compatibility... 2-62 Raven-Detected Errors ... 2-63 Timers ... 2-63 Interrupt Delivery Modes ... 2-64 Block Diagram Description... 2-65 Program-Visible Registers ... 2-66 Interrupt Pending Register (IPR) ... 2-66 Interrupt Selector (IS) ...
Page 11 8259 Mode...2-90 Current Task Priority Level...2-90 Architectural Notes ...2-91 CHAPTER 3 Falcon ECC Memory Controller Chip Set Introduction...3-1 Features ...3-1 Block Diagrams ...3-2 Functional Description...3-5 Bit Ordering Convention ...3-5 Performance ...3-5 Four-beat Reads/Writes ...3-5 Single-beat Reads/Writes ...3-6 DRAM Speeds ...3-6 ROM/Flash Speeds ...3-10 PowerPC 60x Bus Interface...3-11 Responding to Address Transfers...3-11...
Page 12 DRAM Attributes Register ... 3-33 DRAM Base Register... 3-35 CLK Frequency Register... 3-35 ECC Control Register ... 3-36 Error Logger Register ... 3-39 Error Address Register ... 3-42 Scrub/Refresh Register... 3-43 Refresh/Scrub Address Register ... 3-44 ROM A Base/Size Register... 3-45 ROM B Base/Size Register ...
Page 13 Role of the Raven ASIC ...5-13 PCI Domain ...5-13 PCI-SCSI ...5-13 PCI/Ethernet ...5-13 PCI-Graphics ...5-14 Role of the Universe ASIC ...5-14 VMEbus Domain ...5-14 ROM/Flash Initialization ...5-15 APPENDIX A Related Documentation Motorola Computer Group Documents ...A-1 Manufacturers’ Documents...A-2 Related Specifications...A-4 xiii...
Page 15 List of Figures Figure 1-1. MVME2300 Series System Block Diagram ...1-5 Figure 1-2. VMEbus Master Mapping...1-20 Figure 1-3. VMEbus Slave Mapping ...1-22 Figure 1-4. General-Purpose Software-Readable Header...1-32 Figure 2-1. Raven Block Diagram ...2-3 Figure 2-2. MPC-to-PCI Address Decoding...2-5 Figure 2-3. MPC to PCI Address Translation ...2-6 Figure 2-4.
Page 17 List of Tables Table 1-1. Features: MVME2300 Series...1-2 Table 1-2. Default Processor Memory Map...1-8 Table 1-3. CHRP Memory Map Example...1-9 Table 1-4. Raven MPC Register Values for CHRP Memory Map...1-10 Table 1-5. PREP Memory Map Example...1-11 Table 1-6. Raven MPC Register Values for PREP Memory Map ...1-12 Table 1-7.
Page 18 Table 3-4. PowerPC Bus to DRAM Access Timing — 50ns Hyper Devices ... 3-9 Table 3-5. PowerPC 60x Bus to ROM/Flash Access Timing — 64 Bits (32 Bits per Falcon) ... 3-10 Table 3-6. PowerPC 60x Bus to ROM/Flash Access Timing — 16 Bits (8 Bits per Falcon) ...
Page 19: About This Manual
MVME2300 and MVME2300SC series of VME processor modules. The MVME2300 series VME processor module is based on an MPC603 or MPC604 PowerPC microprocessor, and features dual PCI Mezzanine Card (PMC) slots with front panel and/or P2 I/O. In addition, the...
Page 20: Summary Of Changes
This manual is intended for anyone who designs OEM systems, adds capability to an existing compatible system, or works in a lab environment for experimental purposes. A basic knowledge of computers and digital logic is assumed. To use this manual, you may also wish to become familiar with the publications listed in Documentation.
Page 21: Overview Of Contents
Overview of Contents Chapter 1, Board Description and Memory level hardware features of MVME2300 series VME processor modules. It includes memory maps and a discussion of some general software considerations such as cache coherency, interrupts, and bus errors. Chapter 2, Raven PCI Bridge local bus/PowerPC processor bus interface chip used on MVME2300 series boards.
Page 22: Conventions Used In This Manual
In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.
Page 23 Refer to Endian Issues in Chapter 5 for a discussion of which elements on MVME2300 series boards use big-endian byte ordering, and which use small-endian byte ordering. The terms control bit and status bit are used extensively in this document.
Page 24 indicate that the bit is in the state that disables the function it controls. In all tables, the terms 0 and 1 are used to describe the actual value that should be written to the bit, or the value that it yields when read. The term status bit is used to describe a bit in a register that reflects a specific condition.
Page 25: Introduction
MVME2300-series VME processor modules. The chapter begins with a board level overview and features list. Memory maps are next, and are the major feature of this chapter. Programmable registers that reside in ASICs in the MVME2300 series are covered in the chapters on those ASICs. ASIC...
Page 26: Summary Of Features
Board Description and Memory Maps Summary of Features There are many models based on the MVME2300 series architecture. The following table summarizes the major features of the MVME2300 series: Feature Microprocessor Form factor ECC DRAM Flash memory Real-time clock Switches...
Page 27: System Block Diagram
D16/D32/D64) System Block Diagram The MVME2300 series does not provide any look-aside external cache option. The Falcon chip set controls the boot Flash and the ECC DRAM. The Raven ASIC functions as the 64-bit PCI host bridge and the MPIC interrupt controller.
Page 28 Standard I/O functions are provided by the UART device which resides on the ISA bus. The NVRAM/RTC also resides on the ISA bus. The general system block diagram for MVME2300 series is shown below: Computer Group Literature Center Web Site...
Page 29: Figure 1-1. Mvme2300 Series System Block Diagram
DEBUG CONNECTOR GENERATOR PROCESSOR MPC603/604 PHB & MPIC RAVEN ASIC ETHERNET DEC21140 PC16550 UART Figure 1-1. MVME2300 Series System Block Diagram http://www.motorola.com/computer/literature 16/32/64/128MB 3MB or 5MB SYSTEM REGISTERS MEMORY CONTROLLER FALCON CHIP SET 33MHz 32/64-BIT PCI LOCAL BUS VME BRIDGE...
Page 30: Functional Description
ISA bus are: one asynchronous serial port, a real-time clock, counters/timers, and a software-readable header. VMEbus Interface MVME2300 series boards interface to the VMEbus via the P1 and P2 backplane connectors. MVME2300SC boards use the three-row 96-pin connectors specified in the original VMEbus standard; non-SCbus MVME2300 boards use the 5-row 160-pin connectors specified in the VME64 Extension standard.
Page 31: Pci Interface
The Processor memory map is controlled by the Raven ASIC and the Falcon chip set. The Raven ASIC and the Falcon chip set have flexible programming Map Decoder registers to customize the system for many different applications. http://www.motorola.com/computer/literature Programming Model...
Page 32: Default Processor Memory Map
Board Description and Memory Maps Default Processor Memory Map After a reset, the Raven ASIC and the Falcon chip set provide the default processor memory map as shown in the following table. Table 1-2. Default Processor Memory Map Processor Address Start 0000 0000 7FFF FFFF...
Page 33: Processor Chrp Memory Map
FFF0 0000 FFFF FFFF Notes 1. Programmable via Falcon chip set. For the MVME2300 series, RAM size is limited to 128MB and ROM/Flash to 4MB. 2. To enable the “Processor-hole” area, program the Falcon chip set to ignore 0x000A0000 - 0x000BFFFF address range and program the Raven to map this address range to PCI memory space.
Page 34: Table 1-4. Raven Mpc Register Values For Chrp Memory Map
Board Description and Memory Maps 3. Programmable via Raven ASIC. 4. CHRP requires the starting address for the PCI memory space to be 5. Programmable via Raven ASIC for either contiguous or spread-I/O 6. The actual size of each ROM/Flash bank may vary. 7.
Page 35: Processor Prep Memory Map
Processor PREP Memory Map The Raven/Falcon chip set can be programmed for PREP-compatible memory map. The following table shows the PREP memory map of the MVME2300 series from the point of view of the processor. Table 1-5. PREP Memory Map Example Processor Address...
Page 36: Pci Configuration Access
Board Description and Memory Maps 4. The first Megabyte of ROM/Flash bank A appears at this range after 5. This range can be mapped to the VMEbus by programming the 6. The only method of generating a PCI Interrupt Acknowledge cycle The following table shows the programmed values for the associated Raven MPC registers for the processor PREP memory map.
Page 37: Pci Memory Maps
Software must program the appropriate map decoders for a specific environment. PCI CHRP Memory Map The following table shows a PCI memory map of the MVME2300 series that is CHRP-compatible from the point of view of the PCI local bus. Table 1-7. PCI CHRP Memory Map...
Page 38 PCI Memory Space PCI Memory Space or System Memory Alias Space (mapped to 00000000 to 00FFFFFF) Reserved MVME2300 series, RAM size is limited to 128MB. 0x000A0000 - 0x000FFFFF address range. Universe ASIC. Universe ASIC. Computer Group Literature Center Web Site...
Page 39: Table 1-8. Raven Pci Register Values For Chrp Memory Map
Table 1-9. Universe PCI Register Values for CHRP Memory Map Configuration Address Offset $100 $104 $108 $10C $114 $118 $11C http://www.motorola.com/computer/literature Register Value (Aliasing OFF) FC00 0000 0000 3FFF 0000 00FX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000...
Page 40: Pci Prep Memory Map
$13C $140 $144 $148 $188 PCI PREP Memory Map The following table shows a PCI memory map of the MVME2300 series boards that is PREP-compatible from the point of view of the PCI local bus. PCI Address Start 0000 0000...
Page 41 64M - 256K Notes 1. Programmable via the Raven’s PCI Configuration registers. For the MVME2300 series, RAM size is limited to 128MB. 2. To enabled the CHRP “io-hole”, program the Raven to ignore the 0x000A0000 - 0x000FFFFF address range. 3. Programmable mapping via the four PCI Slave Images in the Universe ASIC.
Page 42: Table 1-11. Raven Pci Register Values For Prep Memory Map
Board Description and Memory Maps The following table shows the programmed values for the associated Raven PCI registers for the PREP-compatible memory map. Table 1-11. Raven PCI Register Values for PREP Memory Map Configuration Address Offset 1-18 Configuration Register Value Register Name RavenMPIC MBASE FC00 0000...
Page 43: Table 1-12. Universe Pci Register Values For Prep Memory Map
$104 $108 $10C $114 $118 $11C $120 $128 $12C $130 $134 $13C $140 $144 $148 $188 http://www.motorola.com/computer/literature Configuration Register Value Register Name LSI0_CTL C082 5100 LSI0_BS 0100 0000 LSI0_BD 3000 0000 LSI0_TO XXXX 0000 LSI1_CTL C042 5100 LSI1_BS 3000 0000...
Page 44: Vmebus Mapping
Universe ASIC’s address translation capabilities. The Processor Memory Map section shows the recommended mapping. VMEbus Master Map The figure below illustrates how VMEbus master mapping is accomplished. (Note that for MVME2300 series boards, RAM size is limited to 128MB.) PROCESSOR ONBOARD...
Page 45: Vmebus Slave Map
VMEbus. In most applications, the VMEbus needs to see only the system memory and, perhaps, the software interrupt registers (SIR1 and SIR2 registers). For an example of the VMEbus slave map, refer to the figure below: http://www.motorola.com/computer/literature Programming Model 1-21...
Page 46: Figure 1-3. Vmebus Slave Mapping
Board Description and Memory Maps Processor Onboard Memory ISA Space Software INT Registers Notes 1. Programmable mapping via the four VME Slave Images in the 2. Programmable mapping via PCI Slave Images in the Raven ASIC. 3. Fixed mapping via the PIB device. 1-22 PCI Memory NOTE 2...
Page 47: Table 1-13. Universe Pci Register Values For Vmebus Slave Map Example
$F00 $F04 $F08 $F0C $F14 $F18 $F1C $F20 $F28 $F2C $F30 $F34 $F3C $F40 $F44 $F48 http://www.motorola.com/computer/literature Register Value (CHRP) VSI0_CTL C0F2 0001 VSI0_BS 4000 0000 VSI0_BD 4000 1000 VSI0_TO C000 1000 VSI1_CTL E0F2 00C0 VSI1_BS 1000 0000 VSI1_BD 2000 0000...
Page 48: Falcon-Controlled System Registers
In addition, the Falcon chip set performs the decode and control for an external register port. This function is utilized by MVME2300 series boards to provide the system control registers. BIT # ---->...
Page 49: System Configuration Register (Syscr)
System Identification. This field specifies the type of the overall system configuration so that the software may appropriately handle any software visible differences. For the MVME2300 series, this field returns a value of $FD. speed and the PCI clock speed information as follows: System Clock Speed...
Page 50 P0/1STAT Value 0B0000 to 0B0011 0B1000 to 0B1111 1-26 System External Cache Size. The MVME2300 series does not offer any external caching options. Reads from this field will always return a hardwired value of 0b1111 indicating the absence of external caching.
Page 51: Memory Configuration Register (Memcr)
Memory Configuration Register - $FEF80404 FIELD OPER RESET M_SIZE[0:1] M_FREF Block A/B/C/D Fast Refresh. When this bit is set, it http://www.motorola.com/computer/literature Memory Size. This field is encoded as follows: M_SIZE[0:1] Total Memory On Board 0B00 0B01 0B10 0B11 indicates that a DRAM block requires faster refresh rate.
Page 52 Board Description and Memory Maps M_SPD[0:1] R_A/B_TYP[0:2] ROM_A/B_TYP[0:2] 0B000 to 0B101 Note L2_TYPE[0:3] 1-28 Memory Speed. This field relays the memory speed information as follows: M_SPD[0:1] DRAM Speed 0B00 0B01 0B10 0B11 These two bits reflect the combined status of the four blocks of DRAM.
Page 53: System External Cache Control Register (Sxccr)
The MVME2300 and MVME2300SC boards do not implement this register. Writes to this register location ($FEF88000) will have no system effects. Reads from this register location will return undefined data. http://www.motorola.com/computer/literature L2 Core Frequency to L2 Frequency divider. This field is encoded as follows:...
Page 54: Processor 0 External Cache Control Register (P0Xccr)
Board Description and Memory Maps Processor 0 External Cache Control Register (P0XCCR) The MVME2300 and MVME2300SC boards do not implement this register. Writes to this register location ($FEF88100) will have no system effects. Reads from this register location will return undefined data. Processor 1 External Cache Control Register (P1XCCR) The MVME2300 and MVME2300SC boards do not implement this register.
Page 55: Isa Local Resource Bus
PCI bus. Refer to the W83C553 Data Book for details. 16550 UART The 16550 UART provides the MVME2300 series boards with an asynchronous serial port. Refer to the 16550 Data Sheet for additional details and programming information.
Page 56: General-Purpose Readable Jumpers
Figure 1-4. Figure 1-4. General-Purpose Software-Readable Header NVRAM/RTC and Watchdog Timer Registers The M48T59/559 provides the MVME2300 series boards with 8K of non- volatile SRAM, a time-of-day clock, and a watchdog timer. Accesses to the M48T59/559 are accomplished via three registers:...
Page 57: Module Configuration And Status Registers
Table 1-18. Module Configuration and Status Registers PCI I/O Address 0000 0800 0000 0802 0000 0803 0000 08C0 - 0000 08C1 http://www.motorola.com/computer/literature Function NVRAM/RTC Address Strobe 0 (A7 - A0) NVRAM/RTC Address Strobe 1 (A15 - A8) NVRAM/RTC Data Register Function...
Page 58: Cpu Configuration Register
CPU Configuration Register The CPU Configuration register is an 8-bit register located at ISA I/O address x0800. This register is defined for the MVME2300 series to provide some backward compatibility with older MVME1600 products. The Base Module Status register should be used to identify the base module type and the System Configuration register should be used to obtain information about the overall system.
Page 59: Base Module Feature Register
PMC2P_ PMC Slot 2 present. If set, there is no PCI Mezzanine PMC1P_ PMC Slot 1 present. If set, there is no PCI Mezzanine VMEP_ LANP_ http://www.motorola.com/computer/literature PCI Expansion Slot present. If set, there is no PCIX device installed. If cleared, the PCIX slot contains a PCI Mezzanine Card.
Page 60: Base Module Status Register (Bmsr)
Board Description and Memory Maps Base Module Status Register (BMSR) The Base Module Status register is an 8-bit read-only register located at ISA I/O address x0803. FIELD OPER RESET BASE_TYPE 1-36 Base Module Status Register - Offset $0803 Base Module Type. This four-bit field is used to provide the category of the base module and is defined as follows: BASE_TYPE Value $0 to $8...
Page 61: Seven-Segment Display Register
For these registers to be accessible from the VMEbus, the Universe ASIC must be programmed to map VMEbus Slave Image 0 into the appropriate PCI I/O address range. Refer to the additional details. http://www.motorola.com/computer/literature DIG2[3:0] DIG1[3:0] VMEbus Slave Map ISA Local Resource Bus...
Page 62: Lm/Sig Control Register
Board Description and Memory Maps PCI I/O Address 0000 1000 0000 1001 0000 1002 0000 1003 0000 1004 0000 1005 0000 1006 These registers are described in the following subsections. LM/SIG Control Register The LM/SIG Control register is an 8-bit register located at ISA I/O address x1000.
Page 63: Lm/Sig Status Register
EN_SIG1 When the EN_SIG1 bit is set, an LM/SIG Interrupt 1 is EN_SIG0 When the EN_SIG0 bit is set, an LM/SIG Interrupt 0 is http://www.motorola.com/computer/literature Writing a 1 to this bit will set the LM1 status bit. Writing a 1 to this bit will set the LM0 status bit.
Page 64 Board Description and Memory Maps EN_LM1 When the EN_LM1 bit is set, an LM/SIG Interrupt 1 is EN_LM0 When the EN_LM0 bit is set, an LM/SIG Interrupt 0 is SIG1 SIG0 1-40 generated and the LM1 bit is asserted. generated and the LM0 bit is asserted. SIG1 status bit.
Page 65: Location Monitor Upper Base Address Register
VMEbus to provide VMEbus location monitor function. Location Monitor Lower Base Address Register - Offset $1003 FIELD OPER RESET VA[7:4] LMEN http://www.motorola.com/computer/literature VA13 VA12 VA11 VA10 Upper Base Address for the location monitor function. LMEN Lower Base Address for the location monitor function.
Page 66: Semaphore Register 1
Board Description and Memory Maps Semaphore Register 1 Semaphore Register 1 is an 8-bit register located at ISA I/O address x1004. The Universe ASIC is programmed so that this register can be accessible from the VMEbus. This register can only be updated if bit 7 is low or if the new value has the most significant bit cleared.
Page 67: Vme Geographical Address Register (Vgar)
RESET Emulated Z8536 CIO Registers and Port Pins Although MVME2300 series boards do not use a Z8536 device, several of its functions are emulated within an ISA Register PLD. These functions are accessed by reading/writing the Port A, B, C Data registers and Control register.
Page 68: Z8536 Cio Port Pins
Board Description and Memory Maps Z8536 CIO Port Pins The following table shows the signal function and port mapping for the Z8536 CIO emulation. The signal directions are fixed in hardware. Table 1-21. Z8536 CIO Port Pin Assignments Port Signal Name BRDFAIL ABORT_...
Page 69: Isa Dma Channels
Name BASETYP0 Input BASETYP1 Input ISA DMA Channels No ISA DMA channels are implemented on MVME2300 series boards. http://www.motorola.com/computer/literature ISA Local Resource Bus Descriptions Genesis Base Module Type: 00b = Genesis II (see Base Module Status Register) 01b = MVME1600-011...
Page 71: Introduction
2Raven PCI Bridge ASIC Introduction This chapter describes the architecture and usage of the Raven ASIC, a PowerPC-to-PCI-Local-Bus bridge controller chip. The Raven is intended to provide PowerPC 60x (MPC60x) compliant devices access to devices residing on the PCI Local Bus. In the remainder of this chapter, the MPC60x bus is referred to as the "MPC bus"...
Page 72: Block Diagram
Raven PCI Bridge ASIC Table 2-1. Features of the Raven ASIC (Continued) Function Interrupt Controller Processor Coordination Block Diagram Figure 2-1 Raven control logic is subdivided into the following functions: Features MPIC compliant Support for 16 external interrupt sources and two processors Multiprocessor interrupt control allowing any interrupt source to be directed to either processor Multilevel cross-processor interrupt control for multiprocessor...
Page 73: Figure 2-1. Raven Block Diagram
Block Diagram 1914 9702 Figure 2-1. Raven Block Diagram http://www.motorola.com/computer/literature...
Page 74: Functional Description
Raven PCI Bridge ASIC Functional Description The Raven data path logic is subdivided into the following functions: Address decoding is handled in the PCI Decode and MPC Decode blocks. The control register logic is contained in the PCI Registers and MPC Registers blocks.
Page 75: Figure 2-2. Mpc-To-Pci Address Decoding
16 most significant bits of the MPC address, and the result is used as the PCI address. This offset allows PCI devices to reside at any PCI address, independent of the MPC address map. An example of this appears in Figure 2-3. http://www.motorola.com/computer/literature...
Page 76: Mpc Slave
Raven PCI Bridge ASIC MPC Bus Address MSOFFx Register PCI Bus Address Figure 2-3. MPC to PCI Address Translation You should take care to assure that all programmable decoders decode unique address ranges, since overlapping address ranges will lead to undefined operation.
Page 77: Table 2-2. Command Types - Mpc Slave Response
TLBSYNC ICBI Reserved Write-with-flush Write-with-kill Read Read-with-intent-to-modify Write-with-flush-atomic Reserved Read-atomic Read-with-intent-to-modify-atomic Reserved Reserved Read-with-no-intent-to-cache Reserved Reserved http://www.motorola.com/computer/literature Functional Description Transfer Transaction Encoding 00000 Addr Only 00100 Addr Only 01000 Addr Only 01100 Addr Only 10000 Addr Only 10100 No Response...
Page 78: Mpc Write Posting
Raven PCI Bridge ASIC MPC Write Posting The MPC write FIFO stores up to eight data beats in any combination of single- and four-beat (burst) transactions. If write-posting is enabled, Raven stores the data necessary to complete an MPC write transfer to the PCI bus and immediately acknowledges the transaction on the MPC bus.
Page 79: Table 2-3. Mpc Transfer Types
The MPC master incorporates an optional operating mode called Bus Hog. When Bus Hog is enabled, the MPC master will continually request the MPC bus for the entire duration of each PCI transfer. When Bus Hog is not http://www.motorola.com/computer/literature Table 2-3 shows the relationship between PCI command...
Page 80: Mpc Arbiter
BHOG bit within the GCSR. The default state for BHOG is disabled. MPC Arbiter The MPC Arbiter is an optional feature in the Raven ASIC. It is not used on MVME2300 series boards. Arbitration for the MPC bus on the MVME2300 series is performed external to the Raven. MPC Bus Timer The MPC bus timer allows the current bus master to recover from a lock- up condition resulting from no slave response to the transfer request.
Page 81: Pci Address Mapping
64-byte header. These control registers support a mapping scheme that is functionally similar to the PCI-to-MPC mapping scheme described in the section on MPC Address Mapping http://www.motorola.com/computer/literature Functional Description earlier in this chapter. 2-11...
Page 82: Figure 2-4. Pci To Mpc Address Decoding
Raven PCI Bridge ASIC MPC Bus Address Space The Raven will map MPC address space into PCI Memory space using four programmable map decoders. The most significant 16 bits of the PCI address are compared with the address range of each map decoder; if the address falls within the specified range, the access is passed on to the MPC bus.
Page 83: Figure 2-5. Pci To Mpc Address Translation
PCI I/O space using traditional PCI-defined base registers within the predefined 64-byte header. Refer to the section on Controller for more information. http://www.motorola.com/computer/literature 8 0 8 0 1 2 3 4 9 0 0 0 1 0 8 0 1 2 3 4...
Page 84: Pci Slave
Raven PCI Bridge ASIC PCI Slave The PCI slave provides the control logic needed to interface the PCI bus to the Raven’s FIFO buffers. The PCI slave can accept either 32-bit or 64-bit transactions, but it can accept only 32-bit addressing. There is no limit to the length of the transfer that the slave can handle.
Page 85: Table 2-4. Command Types - Pci Slave Response
During I/O read cycles, the slave will perform integrity checking of the byte enables against the address being presented and assert SERR in the event there is an error. http://www.motorola.com/computer/literature Functional Description Slave Response? 2-15...
Page 86 Raven PCI Bridge ASIC The slave will honor only the Linear Incrementing addressing mode. The slave will perform a disconnect with data if any other mode of addressing is attempted. Device Selection The PCI slave will always respond to valid decoded cycles as a medium responder.
Page 87: Pci Write Posting
PCI bus has 64-bit mode enabled. If at any time during the transaction the PCI target indicates that it cannot support 64-bit mode, the PCI master will continue to transfer the remaining data in 32-bit mode. http://www.motorola.com/computer/literature Functional Description 2-17...
Page 88: Table 2-5. Pci Master Command Codes
Raven PCI Bridge ASIC The PCI master can support Critical Word First (CWF) burst transfers. The PCI master will divide this transaction into two parts. The first part will start on the address presented with the CWF transfer request and continue up to the end of the current cache line.
Page 89 1s. If the PCI master detects a target abort during a write, any untransferred portions of data will be dropped. The same rule applies if the PCI master generates a Master Abort cycle. http://www.motorola.com/computer/literature Functional Description TBST...
Page 90 Raven PCI Bridge ASIC Arbitration The PCI master can support parking on the PCI bus. If the PCI master starts a transaction that is going to take more than one beat, the PCI master will continuously assert its request until the transaction has completed. The one exception is when the PCI master receives a disconnect or a retry.
Page 91: Generating Pci Cycles
The Raven will perform contiguous I/O addressing when the MEM bit is clear and the IOM bit is clear. The Raven will take the MPC address, apply the offset specified in the MSOFFx register, and map the result directly to PCI. http://www.motorola.com/computer/literature PCI Cycle Type Memory Contiguous I/O...
Page 92: Figure 2-6. Pci Spread I/O Address Translation
Raven PCI Bridge ASIC The Raven will perform spread I/O addressing when the MEM bit is clear and the IOM bit is set. The Raven will take the MPC address, apply the offset specified in the MSOFFx register, and map the result to PCI as shown in MPC Address + Offset 25 24...
Page 93 When performing a configuration cycle, the Raven uses the upper 20 address bits as IDSEL lines. During the address phase of a configuration cycle, only one of the upper address bits will be set. The device that has its http://www.motorola.com/computer/literature Functional Description 2-23...
Page 94 Raven PCI Bridge ASIC IDSEL connected to the address bit being asserted will be selected for a configuration cycle. The Raven decodes the Device Number to determine which of the upper address lines to assert. The decoding of the five-bit Device Number is show below:.
Page 95: Endian Conversion
PCI bus must be swapped such that the PCI bus looks big-endian from the MPC bus’s perspective. This association is true regardless of whether the transaction originates on the PCI bus or the MPC bus. illustrates the concept. http://www.motorola.com/computer/literature Functional Description Figure 2-7 2-25...
Page 96: Figure 2-7. Big- To Little-Endian Data Swap
Raven PCI Bridge ASIC Figure 2-7. Big- to Little-Endian Data Swap 2-26 32-bit PCI Computer Group Literature Center Web Site PPC Bus 64-bit PCI PPC Bus 1916 9610...
Page 97: Table 2-6. Address Modification For Little-Endian Transfers
With respect to the MPC bus (but not always the address internal to the processor), the MPC registers are always represented in big-endian mode. This means that the processor’s internal view of the MPC registers will vary depending on the processor’s operating mode. http://www.motorola.com/computer/literature Data Address Length Modification...
Page 98: Error Handling
Raven PCI Bridge ASIC With respect with the PCI bus, the RavenMPIC registers and the configuration registers are always represented in little-endian mode. The CONFIG_ADDRESS and CONFIG_DATA registers are actually represented in PCI space to the processor and are subject to the endian functions.
Page 99: Transaction Ordering
The Raven ASIC supports transaction ordering with an optional FIFO flushing option. The FLBRD (Flush Before Read) bit within the GCSR register controls the flushing of PCI write-posted data when performing MPC-originated read transactions. http://www.motorola.com/computer/literature Error Address and Attributes MATO...
Page 100: Raven Registers
Raven PCI Bridge ASIC When the FLBRD bit is set, Raven will handle read transactions originating from the MPC bus in the following manner: Raven Registers This section provides a detailed description of all registers in the Raven ASIC. The registers are organized in two groups: MPC registers and PCI Configuration registers.
Page 101: Table 2-7. Raven Mpc Register Map
$FEFF0024 $FEFF0028 $FEFF002C $FEFF0030 $FEFF0034 $FEFF0038 $FEFF003C $FEFF0040 $FEFF0044 MSOFF0 $FEFF0048 $FEFF004C MSOFF1 $FEFF0050 $FEFF0054 MSOFF2 $FEFF0058 $FEFF005C MSOFF3 http://www.motorola.com/computer/literature REVID GCSR MERAD PIACK MSADD0 MSADD1 MSADD2 MSADD3 Raven Registers DEVID FEAT MARB PADJ MEREN MERST MERAT MSATT0 MSATT1 MSATT2...
Page 102: Vendor Id/Device Id Registers
Vendor ID. Identifies the manufacturer of the device. The identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the PCI Configuration registers. Device ID. Identifies this particular device. The Raven will always return $4801.
Page 103: Revision Id Register
0 1 2 3 4 5 6 7 8 9 Name GCSR Operation Reset LEND http://www.motorola.com/computer/literature $FEFF0004 REVID Revision ID. Identifies the Raven revision level. This register is duplicated in the PCI Configuration registers. $FEFF0008 Endian Select. If set, the MPC bus is operating in little- endian mode.
Page 104 Raven PCI Bridge ASIC FLBRD BHOG MBTx MARB MPIC 2-34 Flush Before Read. If set, the Raven will guarantee that all PCI-initiated posted write transactions will complete before any MPC-initiated read transactions are allowed to complete. When FLBRD is clear, there is no correlation between these transaction types and their order of completion.
Page 105 MIDx FEAT http://www.motorola.com/computer/literature Master ID. Encoded as shown below to indicate who is currently the MPC bus master. When the internal MPC arbiter is enabled (MARB is set), these bits are controlled by the internal arbiter. When the internal arbiter is disabled (MARB is clear) these bits reflect the status of the CPUID pins.
Page 106: Mpc Arbiter Control Register
MPC Arbiter Control Register Address 0 1 2 3 4 5 6 7 8 9 Name Operation Reset This register is not used in MVME2300 series boards. Prescaler Adjust Register Address 0 1 2 3 4 5 6 7 8 9 Name Operation...
Page 107: Mpc Error Enable Register
DFLT MATOM MPC Address Bus Time-out Machine Check Enable. PERRM SERRM http://www.motorola.com/computer/literature $FEFF0020 Default MPC Master ID. This bit determines which MCHK pin will be asserted for error conditions in which the MPC master ID cannot be determined or the Raven was the MPC master.
Page 108 Raven PCI Bridge ASIC SMAM RTAM MATOI PERRI SERRI SMAI RTAI 2-38 PCI Signalled Master Abort Machine Check Enable. When this bit is set, the SMA bit in the MERST register is used to assert the MCHK output to the bus master which initiated the transaction.
Page 109: Mpc Error Status Register
Operation Reset MATO PERR http://www.motorola.com/computer/literature $FEFF0024 Error Status Overflow. This bit is set when an error is detected and any of the error status bits are already set. The bit may be cleared by writing a 1 to it; writing a 0 to it has no effect.
Page 110: Mpc Error Address Register
Raven PCI Bridge ASIC SERR MPC Error Address Register Address 0 1 2 3 4 5 6 7 8 9 Name Operation Reset 2-40 PCI System Error. This bit is set when the PCI SERR pin is asserted. The bit may be cleared by writing it to a 1; writing it to a 0 has no effect.
Page 111: Mpc Error Attribute Register - Merat
Reset MIDx TBST TSIZx http://www.motorola.com/computer/literature MPC Error Address. This register captures the MPC address when the MATO bit is set in the MERST register. It captures the PCI address when the SMA or RTA bits are set in the MERST register. Its contents are not defined when the PERR or SERR bits are set in the MERST register.
Page 112 Raven PCI Bridge ASIC If the SMA or RTA bits are set, the register is defined by the following figure: Address 0 1 2 3 4 5 6 7 8 9 Name Operation Reset MIDx COMMx PCI Command. Contains the PCI command of the PCI BYTEx 2-42 $FEFF002C...
Page 113: Pci Interrupt Acknowledge Register
$0000 To initiate a PCI cycle from the MPC bus, the MPC address must be greater than or equal to the START field and less than or equal to the END field. http://www.motorola.com/computer/literature $FEFF0030 PIACK $00000000 PCI Interrupt Acknowledge. Performing a read from this register will initiate a single PCI Interrupt Acknowledge cycle.
Page 114: Mpc Slave Address (3) Register
Raven PCI Bridge ASIC START MPC Slave Address (3) Register Address 0 1 2 3 4 5 6 7 8 9 Name Operation Reset MSADD3, MSOFF3 and MSATT3 represent the only register group which can be used to initiate access to the PCI Configuration Address ($80000CF8) and Configuration Data ($80000CFC) registers.
Page 115: Mpc Slave Offset/Attribute (0,1 And 2) Registers
Reset $0000 MSOFFx MPC Slave Offset. A 16-bit offset that is added to the http://www.motorola.com/computer/literature Start Address. Determines the start address of a particular memory area on the MPC bus which will be used to access PCI bus resources. The value of this field will be compared with the upper 16 bits of the incoming MPC address.
Page 116: Mpc Slave Offset/Attribute (3) Registers
Raven PCI Bridge ASIC WPEN MPC Slave Offset/Attribute (3) Registers Address 0 1 2 3 4 5 6 7 8 9 Name Operation Reset MSOFF3 MPC Slave Offset. Contains a 16-bit offset that is added 2-46 Write-Post Enable. If set, write-posting is enabled for the corresponding MPC slave.
Page 117: General-Purpose Registers
PCI Local Bus Specification, Revision 2.0. The CONFIG_ADDRESS and CONFIG_DATA registers described in this section are accessed within PCI I/O space. http://www.motorola.com/computer/literature Read Enable. If set, the corresponding MPC slave is enabled for read transactions.
Page 118: Table 2-8. Raven Pci Configuration Register Map
Raven PCI Bridge ASIC All write operations to reserved registers will be treated as no-ops. That is, the access will be completed normally on the bus and the data will be discarded. Read accesses to reserved or unimplemented registers will be completed normally and a data value of 0 returned.
Page 119: Table 2-9. Raven Pci I/O Register Map
Vendor ID. Identifies the manufacturer of the device. This identifier is allocated by the PCI SIG to ensure uniqueness. $1057 has been assigned to Motorola. This register is duplicated in the MPC registers. Device ID. Identifies the particular device. The Raven will always return $4801.
Page 120: Pci Command/ Status Registers
Raven PCI Bridge ASIC PCI Command/ Status Registers Offset Name Operation Reset IOSP MEMSP MSTR PERR SERR FAST 2-50 PSTAT IO Space Enable. If set, the Raven will respond to PCI I/O accesses when appropriate. If cleared, the Raven will not respond to PCI I/O space accesses.
Page 121 RCVTA RCVMA SIGSE RCVPE http://www.motorola.com/computer/literature Data Parity Detected. This bit is set when three conditions are met: 1) the Raven asserted PERR itself or observed PERR asserted; 2) the Raven was the PCI master for the transfer in which the error occurred; 3) the PERR bit in the PCI Command register is set.
Page 122: Revision Id/ Class Code Registers
Raven PCI Bridge ASIC Revision ID/ Class Code Registers Offset Name Operation Reset REVID CLASS I/O Base Register Offset Name Operation Reset This register controls the mapping of the MPIC control registers in PCI I/O space. IO/MEM IO Space Indicator. This bit is hard-wired to a logic 1 to 2-52 CLASS $060000...
Page 123: Memory Base Register
IO/MEM IO Space Indicator. This bit is hard-wired to a logic 0 to MTYPx MEMBA Memory Base Address. These bits define the memory http://www.motorola.com/computer/literature Reserved. This bit is hard-wired to 0. I/O Base Address. These bits define the I/O space base address of the MPIC control registers.
Page 124: Pci Slave Address (0,1,2 And 3) Registers
Raven PCI Bridge ASIC PCI Slave Address (0,1,2 and 3) Registers Offset Name Operation Reset To initiate an MPC cycle from the PCI bus, the PCI address must be greater than or equal to the START field and less than or equal to the END field. START 2-54 PSADD0 - $80...
Page 125: Pci Slave Attribute/ Offset (0,1,2 And 3) Registers
PSOFFx Operation Reset $0000 RAEN WPEN PSOFFx http://www.motorola.com/computer/literature PSATT0/PSOFF0 - $84 PSATT1/PSOFF1 - $8C PSATT2/PSOFF2 - $94 PSATT3/PSOFF3 - $9C Invalidate Enable. If set, the MPC master will issue a transfer type code which specifies the current transaction should cause an invalidate for each MPC transaction originated by the corresponding PCI slave.
Page 126: Config_Address Register
Raven PCI Bridge ASIC CONFIG_ADDRESS Register The description of the CONFIG_ADDRESS register is presented in three perspectives: from the PCI bus, from the MPC bus in big-endian mode, and from the MPC bus in little-endian mode. Note that the view from the PCI bus is purely conceptual, since there is no way to access the CONFIG_ADDRESS register from the PCI bus.
Page 127 Special Cycles: This field must be written with all 1s. Configuration Cycles: Identifies a target’s physical PCI device number. Refer to the section on Cycles Special Cycles: This field must be written with all 1s. http://www.motorola.com/computer/literature $CFD $CFE CONFIG_ADDRESS Register Number.
Page 128: Config_Data Register
Raven PCI Bridge ASIC CONFIG_DATA Register The description of the CONFIG_DATA register is also presented in three perspectives: from the PCI bus, from the MPC bus in big-endian mode, and from the MPC bus in little-lndian mode. Note that the view from the PCI bus is purely conceptual, since there is no way to access the CONFIG_DATA register from the PCI bus.
Page 129 Perspective from the MPC bus in Little-Endian mode Offset $CF8 Bit (DH) 0 1 2 3 4 5 6 7 8 9 Name Data ‘D’ Operation Reset http://www.motorola.com/computer/literature $CFE $CFD CONFIG_DATA Data ‘C’ Data ‘B’ $CFD $CFE CONFIG_DATA Data ‘B’...
Page 130: Raven Interrupt Controller
Raven PCI Bridge ASIC Raven Interrupt Controller This section describes the general implementation of the Raven Interrupt Controller (RavenMPIC). Features The RavenMPIC has the characteristics listed below. Architecture The Raven PCI Slave implements two address decoders for placing the RavenMPIC registers in PCI IO or PCI Memory space. Access to these registers require MPC and PCI bus mastership.
Page 131: Readability Of Csr
The processor will not receive interrupts with a priority level equal to or lower than its current task priority. Therefore, setting the current task priority to 15 prohibits the delivery of all interrupts to the associated processor. http://www.motorola.com/computer/literature Raven Interrupt Controller 2-61...
Page 132: Nesting Of Interrupt Events
Raven PCI Bridge ASIC Nesting of Interrupt Events A processor is guaranteed never to have an in-service interrupt preempted by an equal- or lower-priority source. An interrupt is considered to be in service from the time its vector is returned during an interrupt acknowledge cycle until an EOI is received for that interrupt.
Page 133: Raven-Detected Errors
The timers may be used for system timing or to generate periodic interrupts. Each timer has four registers which are used for configuration and control. They are: 1. Current Count register 2. Base Count register 3. Vector Priority register 4. Destination register http://www.motorola.com/computer/literature Raven Interrupt Controller 2-63...
Page 134: Interrupt Delivery Modes
Raven PCI Bridge ASIC Interrupt Delivery Modes The direct and distributed interrupt delivery modes are supported. Note that the direct delivery mode has sub modes of multicast or non-multicast. The Interprocessor Interrupts (IPIs) and Timer interrupts operate in the direct delivery mode. The externally sourced or I/O interrupts operate in the distributed mode.
Page 135: Figure 2-8. Ravenmpic Block Diagram
If the preceding section is a satisfactory description of the interrupt delivery modes and the reader is not interested in the logic implementation, this section can be skipped. Selector_1 Figure 2-8. RavenMPIC Block Diagram http://www.motorola.com/computer/literature Interrupt Signals Program Visible...
Page 136: Program-Visible Registers
Raven PCI Bridge ASIC Program-Visible Registers These are the registers which software can access. They are described in detail in the Interrupt Pending Register (IPR) The interrupt signals to the RavenMPIC are qualified and synchronized to the clock by the IPR. If the interrupt source is internal to the Raven ASIC or external with their Sense bit = 0 (edge sensitive), a bit is set in the IPR.
Page 137: Interrupt Request Register (Irr)
Interrupt Acknowledge register is examined. On the other hand, if the interrupt is a direct/multicast class interrupt, there are two bits in the IPR associated with this interrupt: one bit for each processor. http://www.motorola.com/computer/literature Raven Interrupt Controller 2-67...
Page 138 Raven PCI Bridge ASIC Then one of these bits is delivered to each Interrupt Selector. Since this interrupt source can be multicast, each of these IPR bits must be cleared separately when the vector is returned for that interrupt to a particular processor.
Page 139: Table 2-10. Ravenmpic Register Map
Table 2-10. RavenMPIC Register Map FEATURE REPORTING REGISTER 0 GLOBAL CONFIGURATION REGISTER 0 MPIC VENDOR IDENTIFICATION REGISTER PROCESSOR INIT REGISTER http://www.motorola.com/computer/literature Read Only field. Read/Write field. Writing a 1 to this field sets this field. Writing a 1 to this field clears this field.
Page 140 Raven PCI Bridge ASIC TIMER FREQUENCY REPORTING REGISTER TIMER 0 CURRENT COUNT REGISTER TIMER 0 VECTOR-PRIORITY REGISTER TIMER 1 CURRENT COUNT REGISTER TIMER 1VECTOR-PRIORITY REGISTER TIMER 2 CURRENT COUNT REGISTER TIMER 2 VECTOR-PRIORITY REGISTER TIMER 3 CURRENT COUNT REGISTER TIMER 3 VECTOR-PRIORITY REGISTER INT.
Page 141 INT. SRC. 12 DESTINATION REGISTER INT. SRC. 13 VECTOR-PRIORITY REGISTER INT. SRC. 13 DESTINATION REGISTER INT. SRC. 14 VECTOR-PRIORITY REGISTER INT. SRC. 14 DESTINATION REGISTER http://www.motorola.com/computer/literature 0 9 8 7 6 5 4 3 2 1 0 Raven Interrupt Controller $10040 $10050...
Page 142 Raven PCI Bridge ASIC INT. SRC. 15 VECTOR-PRIORITY REGISTER INT. SRC. 15 DESTINATION REGISTER RAVEN DETECTED ERRORS VECTOR-PRIORITY REGISTER RAVEN DETECTED ERRORS DESTINATION REGISTER CURRENT TASK PRIORITY REGISTER PROC. 0 CURRENT TASK PRIORITY REGISTER PROC. 1 2-72 IPI 0 DISPATCH REGISTER PROC. 0 IPI 1 DISPATCH REGISTER PROC.
Page 143: Feature Reporting Register
Feature Reporting Register Offset Name Operation Reset NIRQ NCPU http://www.motorola.com/computer/literature $01000 FEATURE REPORTING NIRQ NCPU $00F NUMBER OF IRQs. The number of the highest external IRQ source supported. The IPI, Timer, and Raven Detected Error interrupts are excluded from this count.
Page 144: Global Configuration Register
Raven PCI Bridge ASIC Global Configuration Register Offset Name Operation Reset 2Raven PCI Bridge ASIC 0Raven Interrupt Controller 2-74 $01020 GLOBAL CONFIGURATION Reset Controller. Writing a 1 to this bit forces the controller logic to be reset. The bit is cleared automatically when the reset sequence is complete.
Page 145: Vendor Identification Register
RavenMPIC implementation, but are defined in the MPIC specification. They are the vendor identification and device ID fields. Processor Init Register Offset Name Operation Reset http://www.motorola.com/computer/literature $01080 VENDOR IDENTIFICATION Stepping. The stepping or silicon revision number is initially 0. $01090 PROCESSOR INIT Processor 1.
Page 146: Ipi Vector/Priority Registers
Raven PCI Bridge ASIC The Soft Reset input to the MPC603 or MPC604 is negative-edge- sensitive. IPI Vector/Priority Registers Offset Name Operation Reset MASK PRIOR VECTOR Interrupt Vector. This vector is returned when the 2-76 IPI 0 - $010A0 IPI 1 - $010B0 IPI 2 - $010C0 IPI 3 - $010D0 IPI VECTOR/PRIORITY...
Page 147: Spurious Vector Register
This register is used to report the frequency (in Hz) of the clock source for the global timers. Following a reset, this register contains zero. For the Raven implementation of MPIC on the MVME2300 series, this register must be written with a value of $7DE290 (that is, 66/8 MHz or 8.25 MHz), which corresponds to a 66MHz MPC bus.
Page 148: Timer Current Count Registers
Raven PCI Bridge ASIC Timer Current Count Registers Offset Name Operation Reset Timer Base Count Registers Offset Name Operation Reset 2-78 Timer 0 - $01100 Timer 1 - $01140 Timer 2 - $01180 Timer 3 - $011C0 TIMER CURRENT COUNT $00000000 Toggle.
Page 149: Timer Vector/Priority Registers
Operation Reset $000 MASK http://www.motorola.com/computer/literature Count Inhibit. Setting this bit to 1 inhibits counting for this timer. Setting the bit to 0 allows counting to proceed. Base Count. This field contains the 31-bit count for this timer. When a value is written into this register and the CI...
Page 150: Timer Destination Registers
Raven PCI Bridge ASIC PRIOR VECTOR Interrupt Vector. This vector is returned when the Timer Destination Registers Offset Name Operation Reset This register indicates the destinations for this timer’s interrupts. Timer interrupts operate in the Directed delivery interrupt mode. This register may specify multiple destinations (multicast delivery).
Page 151: External Source Vector/Priority Registers
Operation Reset $000 MASK SENSE http://www.motorola.com/computer/literature Int Src 0 - $10000 Int Src 2 -> Int Src15 - $10020 -> $101E0 PRIOR Mask. Setting this bit disables any further interrupts from this source. If the mask bit is cleared while the bit associated with this interrupt is set in the IPR, the interrupt request will be generated.
Page 152: External Source Destination Registers
Raven PCI Bridge ASIC PRIOR VECTOR Interrupt Vector. This vector is returned when the External Source Destination Registers Offset Name Operation Reset This register indicates the possible destinations for the external interrupt sources. These interrupts operate in the Distributed interrupt delivery mode.
Page 153: Raven-Detected Errors Vector/Priority Register
$000 MASK SENSE PRIOR VECTOR Interrupt Vector. This vector is returned when the http://www.motorola.com/computer/literature $10200 PRIOR Mask. Setting this bit disables any further interrupts from this source. If the mask bit is cleared while the bit associated with this interrupt is set in the IPR, the interrupt request will be generated.
Page 154: Raven-Detected Errors Destination Register
Raven PCI Bridge ASIC Raven-Detected Errors Destination Register Offset Name Operation Reset This register indicates the possible destinations for the Raven-detected error interrupt source. These interrupts operate in the Distributed interrupt delivery mode. Interprocessor Interrupt Dispatch Registers Offset Name Operation Reset There are four Interprocessor Interrupt Dispatch registers.
Page 155: Interrupt Task Priority Registers
15 masks all interrupts to this processor. Hardware will set the task register to $F when it is reset, or when the Init bit associated with this processor is written to a 1. http://www.motorola.com/computer/literature Processor 1. The interrupt is directed to processor 1. Processor 0. The interrupt is directed to processor 0.
Page 156: Interrupt Acknowledge Registers
Raven PCI Bridge ASIC Interrupt Acknowledge Registers Offset Name Operation Reset On PowerPC-based systems, Interrupt Acknowledge is implemented as a read request to a memory-mapped Interrupt Acknowledge register. Reading the Interrupt Acknowledge register returns the interrupt vector corresponding to the highest-priority pending interrupt. Reading this register also has the following side effects.
Page 157: Programming Notes
Programming Notes This section includes a number of items of information that should prove helpful in programming your MVME2300 series board for a variety of applications. External Interrupt Service The following summarizes how an external interrupt is serviced: 1. An external interrupt occurs.
Page 158: Reset State
Raven PCI Bridge ASIC Reset State After a power-on reset, the RavenMPIC state is as follows: 2-88 interrupt source was the 8259, the interrupt handler issues an EOI request to the RavenMPIC. This resets the In-Service bit for the 8259 within the RavenMPIC and allows it to recognize higher- priority interrupt requests, if any, from the 8259.
Page 159: Interprocessor Interrupts
2. Wait for the activity bit (ACT) for that source to be cleared. 3. Make the desired changes. 4. Unmask the source. This sequence ensures that the vector, priority, destination, and mask information remain valid until all processing of pending interrupts is complete. http://www.motorola.com/computer/literature Raven Interrupt Controller 2-89...
Page 160: Eoi Register
Raven PCI Bridge ASIC EOI Register Each processor has a private EOI register which is used to signal the end of processing for a particular interrupt event. If multiple nested interrupts are in service, the EOI command terminates the interrupt service of the highest priority source.
Page 161: Architectural Notes
(such that it can be accessed as quickly as the MSRee bit defined in the Programming Notes the Task Priority register to be updated synchronously with instruction execution. http://www.motorola.com/computer/literature Raven Interrupt Controller section, for example), should the architecture require 2-91...
Page 163: Table 3-1. Features Of The Falcon Chip Set
3Falcon ECC Memory Controller Introduction The Falcon DRAM controller ASIC is designed for the MVME2300 family of boards. It is used in sets of two to provide the interface between the PowerPC 60x bus (also called MPC60x bus or MPC bus) and a 144-bit ECC-DRAM memory system.
Page 164: Block Diagrams
Falcon ECC Memory Controller Chip Set Block Diagrams Figure 3-1 Figure 3-2 overall DRAM connections. Lower PowerPC Data (32Bits) PowerPC Address & Upper PowerPC Data (32 Bits) Figure 3-1. Falcon Pair Used with DRAM in a System depicts a Falcon pair as it would be connected in a system. shows the Falcon’s internal data paths.
Page 165: Figure 3-2. Falcon Internal Data Paths (Simplified)
Block Diagrams PowerPC DRAM Side Side (64 Bits) Latched D (64 Bits) (64 Bits) (8 Bits) (8 Bits) (8 Bits) Uncorrected Data (64 Bits) 1901 9609 Figure 3-2. Falcon Internal Data Paths (Simplified) http://www.motorola.com/computer/literature...
Page 166: Figure 3-3. Overall Dram Connections
Falcon ECC Memory Controller Chip Set BD_RAS_/CAS_ AC_RAS_/CAS_ RA/OE_/WE_ LOWER FALCON RD0-63 CKD0-7 BD_RAS_/CAS_ AC_RAS_/CAS_ RA/OE_/WE_ UPPER FALCON RD0-63 CKD0-7 Figure 3-3. Overall DRAM Connections DRAM DRAM DRAM BLOCK A BLOCK B BLOCK C LOWER LOWER LOWER DRAM DRAM DRAM BLOCK A BLOCK B BLOCK C...
Page 167: Bit Ordering Convention
The Falcon pair also profits from the fact that PowerPC 60x processors can do address pipelining. Many times while a data cycle is finishing, the PowerPC 60x processor begins a new address cycle. The Falcon pair can begin the next DRAM access earlier when this happens, thus shortening http://www.motorola.com/computer/literature Functional Description...
Page 168: Single-Beat Reads/Writes
Falcon ECC Memory Controller Chip Set the access time. Further savings come when the new address cycle is to an address close enough to the previous one that it falls within the same row in the DRAM array. When this happens, the Falcon pair can transfer the data for the next cycle by cycling CAS without cycling RAS.
Page 169: Table 3-2. Powerpc 60 X Bus To Dram Access Timing - 70Ns Page Devices
AACK_ is asserted. Also, the two numbers shown in the 1st Beat column are for page miss/page hit. 2. In some cases, the numbers shown are averages and specific instances may be longer or shorter. http://www.motorola.com/computer/literature Clock Periods Required For: Beat Beat...
Page 170: Table 3-3. Powerpc 60 X Bus To Dram Access Timing - 60Ns Page Devices
Falcon ECC Memory Controller Chip Set Table 3-3. PowerPC 60 x Bus to DRAM Access Timing — 60ns Page Devices. Access Type 4-Beat Read after Idle (Quad- word aligned) 4-Beat Read after Idle (Quad- word misaligned) 4-Beat Read after 4-Beat Read (Quad-word aligned) 4-Beat Read after 4-Beat Read (misaligned)
Page 171: Table 3-4. Powerpc Bus To Dram Access Timing - 50Ns Hyper Devices
AACK_ is asserted. Also, the two numbers shown in the 1st Beat column are for page miss/page hit. 2. In some cases, the numbers shown are averages and specific instances may be longer or shorter. http://www.motorola.com/computer/literature Clock Periods Required For: Beat Beat...
Page 172: Table 3-5. Powerpc 60X Bus To Rom/Flash Access Timing - 64 Bits (32 Bits Per Falcon)
Falcon ECC Memory Controller Chip Set ROM/Flash Speeds The Falcon pair provides the interface for two blocks of ROM/Flash. Each block can address up to 64MB of memory depending on the width implemented for that block (16 bits or 64 bits). Bank A is 64 bits wide and bank B is 16 bits wide.
Page 173: Powerpc 60X Bus Interface
If the access is a write, the Falcon does not write the data for that access to the DRAM array. Depending upon when the retry occurs however, the Falcon pair may cycle the DRAM even though the data transfer does not happen. http://www.motorola.com/computer/literature Functional Description 3-11...
Page 174: Cache Coherency Restrictions
DRAM, the Falcon pair performs a 144-bit wide read cycle to DRAM, merges in the appropriate PowerPC 60x bus write data, and writes 144 bits back to DRAM. 3-12 The MVME2300 series boards have no L2 cache. × [64+8]). Computer Group Literature Center Web Site...
Page 175: Table 3-7. Error Reporting
“no error” or “single-bit error”, both of which are incorrect. greater) Bit Error Notes 1. No opportunity for error, since no read of DRAM occurs during a four-beat write. http://www.motorola.com/computer/literature Single-Beat Write Four-Beat Write Terminate the PowerPC 60x bus cycle normally.
Page 176: Error Logging
Falcon ECC Memory Controller Chip Set Error Logging ECC error logging is facilitated by the Falcon because of its internal latches. When an error (single- or double-bit) occurs in the DRAMs to which a Falcon is connected, it records the address and syndrome bits associated with the data in error.
Page 177 In order to place code correctly in the ROM/Flash devices, address mapping information is required. addresses map to the ROM/Flash addresses when ROM/Flash is 16 bits wide (8 bits per Falcon). bits wide (32 bits per Falcon). http://www.motorola.com/computer/literature Functional Description Table 3-8 shows how PowerPC 60x Table 3-9...
Page 178: Table 3-8. Powerpc 60X To Rom/Flash Address Mapping - Rom/Flash
Falcon ECC Memory Controller Chip Set Table 3-8. PowerPC 60 x to ROM/Flash Address Mapping — ROM/Flash PowerPC 60x A0-A31 $XX000000 $XX000001 $XX000002 $XX000003 $XX000004 $XX000005 $XX000006 $XX000007 $XX000008 $XX000009 $XX00000A $XX00000B $XX00000C $XX00000D $XX00000E $XX00000F $XXFFFFF8 $XXFFFFF9 $XXFFFFFA $XXFFFFFB $XXFFFFFC $XXFFFFFD $XXFFFFFE...
Page 179: Table 3-9. Powerpc 60X To Rom/Flash Address Mapping - Rom/Flash
$X0000007 $X0000008 $X0000009 $X000000A $X000000B $X000000C $X000000D $X000000E $X000000F $X3FFFFF0 $X3FFFFF1 $X3FFFFF2 $X3FFFFF3 $X3FFFFF4 $X3FFFFF5 $X3FFFFF6 $X3FFFFF7 $X3FFFFF8 http://www.motorola.com/computer/literature ROM/Flash A22-A0 ROM/Flash Device Selected $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000000 $000001 $000001 $000001 $000001 $000001 $000001 $000001 $000001...
Page 180: Refresh/Scrub
Falcon ECC Memory Controller Chip Set Table 3-9. PowerPC 60 x to ROM/Flash Address Mapping — ROM/Flash 64 Bits Wide (32 Bits per Falcon) (Continued) PowerPC 60x A0-A31 $X3FFFFF9 $X3FFFFFA $X3FFFFFB $X3FFFFFC $X3FFFFFD $X3FFFFFE $X3FFFFFF Refresh/Scrub The Refresh/Scrub operation varies according to which DRAM blocks are populated: (A and/or B) but not (C and D);...
Page 181: Blocks A And/Or B Present, Blocks C And/Or D Present
Falcon pair does perform the write unless it encounters a double- bit error during the read. If so enabled, single- and double-bit scrub errors are logged, and the PowerPC 60x bus master is notified via interrupt. http://www.motorola.com/computer/literature Functional Description 3-19...
Page 182: Dram Arbitration
Falcon ECC Memory Controller Chip Set DRAM Arbitration The Falcon pair has 3 different entities that can request use of the DRAM cycle controller: The Falcon pair’s arbiters assign priority with the refresher/scrubber highest, the tester next, and the PowerPC 60x bus lowest. When no requests are pending, the arbiter defaults to providing a PowerPC 60x bus grant.
Page 183: External Register Set
SRAM, and its external register set. The base address of the CSR is hard coded to the address $FEF80000 (or $FEF90000 if the SIO pin is low at reset). http://www.motorola.com/computer/literature Programming Model section of this chapter for a description...
Page 184: Figure 3-4. Data Path For Reads From The Falcon Internal Csrs
Falcon ECC Memory Controller Chip Set Accesses to the CSR are mapped differently depending on whether they are reads or writes. For reads, CSR data read on the upper half of the data bus comes from the upper Falcon while CSR data read on the lower half of the data bus comes from the lower Falcon.
Page 185: Figure 3-5. Data Path For Writes To The Falcon Internal Csrs
CSR write accesses are restricted to a size of 1 or 4 bytes and they must be aligned. Some Tester registers are limited to 4-byte only accesses. Figure through Figure 3-9 show the memory maps for the different kinds of access. http://www.motorola.com/computer/literature 3-23...
Page 186: Figure 3-6. Memory Map For Byte Reads To Csr
Falcon ECC Memory Controller Chip Set $FEF80000 $FEF80001 $FEF80002 $FEF80003 $FEF80004 $FEF80005 $FEF80006 $FEF80007 $FEF80008 $FEF80009 $FEF807FF Figure 3-6. Memory Map for Byte Reads to CSR 3-24 Upper Falcon Upper Falcon Upper Falcon Upper Falcon Lower Falcon Lower Falcon Lower Falcon Lower Falcon Upper Falcon Upper Falcon...
Page 187: Figure 3-7. Memory Map For Byte Writes To Internal Register Set And Test Sram
Both Falcons $FEF80002 $FEF80003 Both Falcons $FEF80004 $FEF80005 $FEF80006 $FEF80007 Both Falcons $FEF80008 Both Falcons $FEF80009 $FEF807FF Figure 3-7. Memory Map for Byte Writes to Internal Register Set http://www.motorola.com/computer/literature Writes not allowed Here and Test SRAM Programming Model 1906 9609 3-25...
Page 188: Figure 3-8. Memory Map For 4-Byte Reads To Csr
Falcon ECC Memory Controller Chip Set $FEF80000 $FEF80004 $FEF80008 $FEF8000C $FEF807FC Figure 3-8. Memory Map for 4-Byte Reads to CSR $FEF80000 $FEF80004 $FEF80008 $FEF8000C $FEF807FC Figure 3-9. Memory Map for 4-Byte Writes to Internal Register Set 3-26 Upper Falcon Lower Falcon Upper Falcon Lower Falcon Lower Falcon...
Page 189: Register Summary
The bit is affected by power-up reset. The bit is affected by local reset. The bit is not affected by reset. The effect of reset on the bit is variable. http://www.motorola.com/computer/literature Table 3-10 describe the registers and their bits in Programming Model...
Page 190: Table 3-10. Register Summary
Falcon ECC Memory Controller Chip Set BIT # ----> FEF80000 FEF80008 FEF80010 FEF80018 RAM A BASE FEF80020 CLK FREQUENCY FEF80028 FEF80030 FEF80038 FEF80040 FEF80048 ROM A BASE FEF80050 ROM B BASE FEF80058 FEF80060 FEF80068 TEST PC FEF80070 FEF80078 FEF80080 FEF80088 FEF80090 FEF80098 3-28...
Page 191 FEF80400 FEF80408 FEF804F8 FEF80500 FEF80508 FEF807F8 FEF80800 FEF80BF8 http://www.motorola.com/computer/literature TEST D1 (Middle 32 Bits) TEST D1 (Lower 32 Bits) TEST D2 (Middle 32 Bits) TEST D2 (Lower 32 Bits) TEST D3 (Middle 32 Bits) TEST D3 (Lower 32 Bits) CTR32...
Page 192: Vendor/Device Register
$FEF80000 VENDID READ ONLY represents the vendor number assigned to Motorola Inc. The current value of VENDID ($1507) is incorrect. The correct vendor ID is $1057. This error is presently handled as an erratum. This read-only register contains the value $4802. It is the device number for the Falcon.
Page 193: Revision Id/ General Control Register
Operation READ ZERO Reset REVID aonly_en isa_hole adis http://www.motorola.com/computer/literature $FEF80008 REVID READ ONLY The REVID bits are hard-wired to indicate the revision level of the Falcon. The values are $01 for the first revision, $02 for the second. Normally, the Falcon pair responds to address-only cycles only if they fall within the address range of one of its enabled map decoders.
Page 194: Table 3-11. Ram Spd1,Ram Spd0 And Dram Type
Falcon ECC Memory Controller Chip Set ram fref ram spd0,ram spd1 Table 3-11. ram spd1 , ram spd0 and DRAM Type ram spd0, ram spd1 chipu 3-32 Some DRAMs require that they be refreshed at the rate of 7.8 s per row rather than the standard 15.6 s per row. If any of the DRAM devices require the higher rate, then the ram fref bit should be left set, otherwise, it can be cleared.
Page 195: Dram Attributes Register
NAME OPERATI RESET ram a/b/c/d en ram a/b/c/d siz0-2 http://www.motorola.com/computer/literature $FEF80010 Control bits that enable accesses to the corresponding block of DRAM when set, and disable them when cleared. These control bits define the size of their corresponding block of DRAM.
Page 196: Table 3-12. Block_A/B/C/D Configurations
Falcon ECC Memory Controller Chip Set Table 3-12. Block_A/B/C/D Configurations ram a/b/c/d Block Size siz0-2 %000 %001 16MB %010 32MB %011 64MB %100 128MB %101 256MB %110 1024MB %111 It is important that all of the ram a/b/c/d siz0-2 bits be set to accurately match the actual size of their corresponding blocks.
Page 197: Dram Base Register
CLK Frequency Register Address Name FREQUENCY Operation READ/WRITE Reset 42 P CLK FREQUENCY http://www.motorola.com/computer/literature $FEF80018 RAM B BASE RAM C BASE READ/WRITE READ/WRITE 0 PL 0 PL These control bits define the base address for their block’s DRAM. RAM A/B/C/D BASE bits 0-7/8-15/16-23/24- 31 correspond to PowerPC 60x address bits 0 - 7.
Page 198: Ecc Control Register
Falcon ECC Memory Controller Chip Set ECC Control Register Address Name Operation Reset refdis rwcb 3-36 The output of the chip prescale counter is used by the refresher/scrubber and the 32-bit counter. After power-up, this register is initialized to $42 (for 66MHz). por is set by the occurrence of power-up reset.
Page 199 (rwcb=0) 32 bits Check-bit View (rwcb=1 http://www.motorola.com/computer/literature So, for example, the check-bits that correspond to the 64 bits of data found in normal mode (rwcb=0) at $00001000-$00001003 and $00001008-$0000100b are written and read in check-bit mode (rwcb=1) at location $00001003.
Page 200 Falcon ECC Memory Controller Chip Set 1. Disable scrub writes by clearing the swen bit if it is set. 2. Stop all DRAM Tester operations by clearing the trun bit. 3. Make sure software is not using DRAM at this point, because while 4.
Page 201: Error Logger Register
Falcon pertains to the upper Falcon, and status read from the lower Falcon pertains to the lower Falcon. http://www.motorola.com/computer/literature When tien is set, the setting of the tpass or the tfail bit causes the INT_ signal pin to pulse true.
Page 202 Falcon ECC Memory Controller Chip Set Unlike most of the other registers, however, it is normal for this status to differ between the two. This is due to the fact that each Falcon is connected to its own set of DRAMs. The upper Falcon can log an error during a cycle and the local Falcon not, or vice-versa.
Page 203 ERROR_SYNDROME esblk0,esblk1 scof SBE COUNT http://www.motorola.com/computer/literature DRAM. If escb is 0, it indicates that the PowerPC 60x bus master was accessing DRAM. Note that the DRAM Tester cannot cause an error to be logged. When set, esen allows errors that occur during scrubs to be logged.
Page 204: Error Address Register
Falcon ECC Memory Controller Chip Set Error Address Register Address Name Operation Reset ERROR_ADDRESS 3Falcon ECC Memory Controller Chip Set 0Programming Model 3-42 bit error (independent of the state of the elog bit). It is cleared by power-up reset and by software writing all 0s to it.
Page 205: Table 3-13. Rtest Encodings
%010 %011 %100 %101 %110 %111 http://www.motorola.com/computer/literature $FEF80040 READ ZERO scrub of the entire DRAM. When these bits reach binary 11, they roll over to binary 00 and continue. They are cleared by power-up reset. When set, swen allows the scrubber to perform write cycles.
Page 206: Refresh/Scrub Address Register
Falcon ECC Memory Controller Chip Set Refresh/Scrub Address Register Address Name Operation Reset ROW ADDRESS COL ADDRESS 3-44 $FEF80048 ROW ADDRESS READ/WRITE These bits form the row address counter used by the refresher/scrubber for all blocks of DRAM. The row address counter increments by one after each refresh/scrub cycle.
Page 207: Rom A Base/Size Register
READ/WRITE Reset $FF0 PL ROM A BASE rom_a_64 http://www.motorola.com/computer/literature $FEF80050 READ ZERO These control bits define the base address for ROM/Flash Block A. ROM A BASE bits 0-11 correspond to PowerPC 60x address bits 0 - 11 respectively. For larger ROM/Flash sizes, the lower significant bits of ROM A BASE are ignored.
Page 208: Table 3-14. Rom Block A Size Encoding
Falcon ECC Memory Controller Chip Set rom a siz rom_a_rv rom_a_rv and rom_b_rv determine which (if either) of Table 3-15. rom_a_rv and rom_b_rv Encoding rom_a_rv 3-46 bits wide, where each Falcon interfaces to 32 bits. rom_a_64 matches the value that was on the CKD2 pin at power-up reset.
Page 209: Table 3-16. Read/Write To Rom/Flash
Write 2,3,5,6,7, 8,32-byte Read http://www.motorola.com/computer/literature When rom a en is set, accesses to Block A ROM/Flash in the address range selected by ROM A BASE are enabled. When rom a en is cleared, they are disabled. enabled. When rom a we is cleared, they are disabled.
Page 210: Rom B Base/Size Register
Falcon ECC Memory Controller Chip Set ROM B Base/Size Register Address Name ROM B BASE Operation READ/WRITE Reset ROM B BASE rom_b_64 3-48 $FEF80058 $FF4 PL These control bits define the base address for ROM/Flash Block B. ROM B BASE bits 0-11 correspond to PowerPC 60x address bits 0-11 respectively.
Page 211: Table 3-17. Rom Block B Size Encoding
When rom b we is set, writes to block B ROM/Flash are http://www.motorola.com/computer/literature rom_b_64 matches the inverse of the value that was on the CKD3 pin at power-up reset. It cannot be changed by software.
Page 212: Dram Tester Control Registers
Falcon ECC Memory Controller Chip Set DRAM Tester Control Registers The tester should not be used by software. The trun and tsse bits (bits 0 and 1 of the register at address $FEF80060) should never be set. Caution 32-Bit Counter Address Name Operation...
Page 213: Power-Up Reset Status Register 1
Chapter 1, especially to (SYSCR) Power-Up Reset Status Register 2 Address Name Operation Reset PR_STAT2 http://www.motorola.com/computer/literature $FEF80400 PR_STAT1 READ PR_STAT1 (power-up reset status) reflects the value that was on the RD0-RD31 signal pins at power-up reset. This register is read-only. Falcon-Controlled System Registers...
Page 214: External Register Set
EXTERNAL REGISTER SET so writes can be to either the upper Falcon, or to the lower Falcon. For descriptions of how these registers are used in the MVME2300 series boards, refer to the Registers section of Chapter 1, especially to...
Page 215: Software Considerations
An exception to this is the ROW_ADDRESS and COL_ADDRESS bits. In any event, however, it is not intended that software write to these bits. http://www.motorola.com/computer/literature Software Considerations Table 3-8 and in Table 3-9.
Page 216: Sizing Dram
Falcon ECC Memory Controller Chip Set As with DRAM, software should not change control register bits that affect ROM/Flash while the affected block is being accessed. This generally means that the ROM/Flash size, base address, enable, write enable, etc. are changed only during initial execution in the reset vector area ($FFF00000 - $FFFFFFFF).
Page 217 4 and 5. 6. If no match is found for any size, then the block is unpopulated and has a size of 0MB. http://www.motorola.com/computer/literature shows how PowerPC addresses correspond to DRAM Software Considerations Table 3-18.
Page 218: Table 3-18. Sizing Addresses
Falcon ECC Memory Controller Chip Set Each size that is checked has a specific set of locations that must be written and read. The following table shows the addresses that go with each size. 1024MB 256MB $00000000 $00000000 $20000000 $02000000 $08000000 $0A000000 Table 3-19.
Page 219: Table 3-20. Syndrome Codes Ordered By Bit In Error
Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rd16 rd17 rd18 rd19 rd20 rd21 rd22 rd23 http://www.motorola.com/computer/literature A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 Table 3-20 Table 3-21 rd32 rd48 rd33 rd49...
Page 220 Falcon ECC Memory Controller Chip Set Table 3-20. Syndrome Codes Ordered by Bit in Error Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome Bit Syndrome rd24 rd25 rd10 rd26 rd11 rd27 rd12 rd28 rd13 rd29 rd14 rd30 rd15 rd31 3-58 rd40 rd56 rd41...
Page 221: Table 3-21. Single-Bit Errors Ordered By Syndrome Code
$51 rd43 $71 rd63 $52 rd40 $72 rd17 $33 rd62 $54 rd59 $74 rd11 $35 rd10 $36 rd61 $58 rd58 $78 rd28 $5D http://www.motorola.com/computer/literature Syn- Syn- Syn- drome drome drome ckd7 $A0 rd42 $81 rd38 $C1 rd41 $82 rd35 $C2...
Page 222: Data Paths
Falcon ECC Memory Controller Chip Set Data Paths Because of the Falcon “pair” architecture, data paths can be confusing. Figure 3-10 PowerPC master to DRAM. tabular format. dl31 PowerPC Data dh31 Figure 3-10. PowerPC Data to DRAM Data Correspondence 3-60 attempts to show the placement of data that is written by a Table 3-22 shows the same information in...
Page 223: Table 3-22. Powerpc Data To Dram Data Mapping
DRAM Array Upper Falcon DRAM Data Bits rd[00:07] rd[08:15] rd[16:23] rd[24:31] rd[32:39] rd[40:47] rd[48:55] rd[56:63] rd[00:07] rd[08:15] rd[16:23] rd[24:31] rd[32:39] rd[40:47]...
Page 225: Introduction
64-bit VMEbus-to-PCI interface in one device. Designed by Tundra Semiconductor Corporation in consultation with Motorola, the Universe is compliant with the VME64 specification and is tuned to the new generation of high-speed processors. The Universe is ideally suited for CPU boards acting as both master and slave in the VMEbus system, and is particularly fitted for PCI local systems.
Page 226: Table 4-1. Features Of The Universe Asic
Universe (VMEbus to PCI) Chip The following table summarizes the characteristics of the Universe ASIC. Table 4-1. Features of the Universe ASIC Function VMEbus Interface PCI Local Bus Interface DMA Controller Additional Functionality Features Fully compliant, high-performance 64-bit VMEbus interface VMEbus transfer rates of 60-70 MB/sec Full VMEbus system controller functionality Integral FIFOs for write-posting to maximize bandwidth utilization...
Page 227: Block Diagram
PCI Bus Interface Interrupter and Interrupt Handler DMA Controller These sections describe the operation of the Universe in terms of the different modules and channels listed above and illustrated in http://www.motorola.com/computer/literature Figure 4-1. Notice that for each interface, Block Diagram Figure...
Page 228: Vmebus Interface
Universe (VMEbus to PCI) Chip PCI Bus Interface Master Slave Interrupts Figure 4-1. Architectural Diagram for the Universe VMEbus Interface This section examines the Universe ASIC’s VMEbus interface function, from the standpoint of the Universe as VMEbus slave as well as VMEbus master.
Page 229: Universe As Vmebus Master
The ADOH cycle is used to implement the VMEbus Lock command, allowing a PCI master to lock VMEbus resources. PCI Bus Interface This section examines the Universe ASIC’s PCI bus interface function, from the standpoint of the Universe as PCI slave as well as PCI master. http://www.motorola.com/computer/literature Functional Description...
Page 230: Universe As Pci Slave
Universe (VMEbus to PCI) Chip Universe as PCI Slave Read transactions from the PCI bus are always processed as coupled. Write transactions may be either coupled or posted, depending upon the setting of the PCI bus slave image. (Refer to PCI Bus Slave Images in the Universe User Manual.) With a posted write transaction, write data is written to a Posted Write Transmit FIFO (TXFIFO) and the PCI bus master receives data acknowledgment from the Universe with zero wait states.
Page 231: Vmebus Interrupt Handling
(PCI to VME, or VME to PCI); only the relative identity of the source and destination bus changes. In a DMA transfer, the Universe gains control of the source bus and reads data into its DMAFIFO. http://www.motorola.com/computer/literature Functional Description...
Page 232: Universe Control And Status Registers (Ucsr)
Universe (VMEbus to PCI) Chip Following specific rules of DMAFIFO operation (refer to FIFO Operation and Bus Ownership in the Universe User Manual), it then acquires the destination bus and writes data from its DMAFIFO. The DMA controller can be programmed to perform multiple blocks of transfers using entries in a linked list.
Page 233: Universe Register Map
Figure 4-2. UCSR Access Mechanisms Universe Register Map Table 4-2 lists the Universe registers by address offset. Tables in the Universe User Manual provide detailed descriptions of each register. http://www.motorola.com/computer/literature VMEbus Configuration and Status Registers (VCSR) UNIVERSE DEVICE SPECIFIC REGISTERS...
Page 234: Table 4-2. Universe Register Map
Universe (VMEbus to PCI) Chip Address offsets in to accesses from the VMEbus side using the VMEbus Register Access Image (Refer to Registers in the Universe User Manual.). For register accesses in CR/CSR space, be sure to add 508KB (0x7F00) to the address offsets provided in the table.
Page 235 PCI Command Error Log Register PCI Address Error Log 194 - 1FC DMA Transfer Control Register DMA Transfer Byte Count Register DMA PCI bus Address Register DMA VMEbus Address Register http://www.motorola.com/computer/literature Functional Description Register Universe Reserved Universe Reserved Universe Reserved Universe Reserved...
Page 236 Universe (VMEbus to PCI) Chip Table 4-2. Universe Register Map (Continued) Offset DMA Command Packet Pointer DMA General Control and Status Register DMA Linked List Update Enable Register 228 - 2FC PCI Interrupt Enable PCI Interrupt Status PCI Interrupt Map 0 PCI Interrupt Map 1 VMEbus Interrupt Enable VMEbus Interrupt Status...
Page 237 VMEbus Register Access Image Control Register VMEbus Register Access Image Base Address VMEbus CSR Control Register VMEbus CSR Translation Offset VMEbus AM Code Error Log VMEbus Address Error Log F90 - FEC http://www.motorola.com/computer/literature Functional Description Register Universe Reserved Universe Reserved Universe Reserved Universe Reserved...
Page 238: Universe Chip Problems After Pci Reset
Universe (VMEbus to PCI) Chip Table 4-2. Universe Register Map (Continued) Offset VMEbus CSR Bit Clear Register VMEbus CSR Bit Set Register VMEbus CSR Base Address Register Register space marked as “Reserved” should not be overwritten. Unimplemented registers return a value of 0 on reads; writes complete normally.
Page 239: Workarounds
How many of the Power-Up (P/U) option bits actually get latched as the Universe manual indicates they should, is uncertain. In any case, the EN bit in the LSI0_CTL register is not latched; on MVME2300 series boards, its P/U state is disabled but is not honored.
Page 240: Examples
Description: After a PCI reset, the LSIO image is still enabled, but the base, bound, and translation offset changes value. Workaround: None." Motorola Firmware Engineering has implemented Method 1 in its firmware workaround in PPCBug debugger release 3.1. Note Examples In this section you will find some representative solutions implemented as workarounds for the Universe PCI reset problem described above.
Page 241: Example 2: Mvme3600 Series Board Acts Differently
Configuration Space register at offset 0x10 is being accommodated and enabled during PCI probing. The PCI probe list is set to d,c,e,f,10. Procedure: 1. After a power-up reset, before the init code has written the registers, the LSI0 register settings are: http://www.motorola.com/computer/literature Functional Description 20000000 4-17...
Page 242 Universe (VMEbus to PCI) Chip 2. Run the init code and the LSI0 registers become: 3. After a bye, before the init code has run: 4. Now try modifying the LSI0 env parameters to match those on the 5. Do NOT run the init code, but press the RESET button, and the 6.
Page 243: Example 3: Universe Chip Is Checked At Tundra
The engineer at Tundra re-ran the simulation based on the information given him. He saw exactly what the Motorola engineers had seen, i.e., that the LSI0_BS, LSI0_BD, and LSI0_TO values changed, as well as the LSI0_CTL fields for program, super, and vct.
Page 244 Universe (VMEbus to PCI) Chip LSI0_CTL register: EN, VAS, LAS LSI0_BS register: Bits [31:28] LSI0_BD register: Bits [31:28] All the other fields in the LSI0 registers are reset to 0, which explains why the PGM and SUPER fields changed, the translation offset reset to 0, etc. 4-20 Computer Group Literature Center Web Site...
Page 245: Table 5-1. Pci Arbitration Assignments
5Programming Details Introduction This chapter discusses details of several programming functions that are not tied to any specific ASIC chip. PCI Arbitration PCI arbitration is performed by the PCI-to-ISA Bridge (PIB) which supports six PCI external PCI masters. The PIB can also be a PCI master for ISA DMA functions.
Page 246: Figure 5-1. Mvme2300 Series Interrupt Architecture
Programming Details Interrupt Handling The interrupt architecture of the MVME2300 series VME processor module is illustrated in the following figure: (8529 Pair) Figure 5-1. MVME2300 Series Interrupt Architecture RavenMPIC SERR_& PERR_ PCI Interrupts ISA Interrupts Computer Group Literature Center Web Site...
Page 247: Table 5-2. Ravenmpic Interrupt Assignments
IRQ9 Level IRQ10 Level IRQ11 Level IRQ12 Level IRQ13 Level http://www.motorola.com/computer/literature for details on the RavenMPIC. The following table Interrupt Source PIB (8259) Falcon-ECC Error PCI-Ethernet Not used Not used PCI-VME INT 0 (Universe LINT0#) PCI-VME INT 1 (Universe LINT1#)
Page 248: Interrupts
Programming Details Table 5-2. RavenMPIC Interrupt Assignments (Continued) MPIC Edge/ Polarity Level IRQ14 Level IRQ15 Notes 1. Interrupt from the PCI/ISA Bridge. 2. Interrupt from the Falcon chip set for a single and/or double bit 3. The mapping of interrupt sources from the VMEbus and Universe 4.
Page 249: Figure 5-2. Pib Interrupt Handler Block Diagram
PIRQ0_ PIRQ Route Control Register PIRQ1_ PIRQ Route Control Register PIRQ2_ PIRQ Route Control Register PIRQ3_ PIRQ Route Control Register Figure 5-2. PIB Interrupt Handler Block Diagram http://www.motorola.com/computer/literature Timer1/Counter0 IRQ1 IRQx IRQ3 IRQ4 IRQ5 IRQ6 IRQx IRQ7 IRQx IRQ8 IRQ9...
Page 250: Table 5-3. Pib Pci/Isa Interrupt Assignments
Programming Details The assignments of the PCI and ISA interrupts supported by the PIB are as follows: Table 5-3. PIB PCI/ISA Interrupt Assignments IRQ0 IRQ1 3-10 IRQ2 IRQ8_ IRQ9 IRQ10 PIRQ0_ IRQ11 PIRQ1_ IRQ12 IRQ13 IRQ14 PIRQ2_ IRQ15 PIRQ3_ IRQ3 IRQ4 IRQ5 IRQ6...
Page 251: Isa Dma Channels
Use this routing for PCI interrupts only when the RavenMPIC is either not present or not used. 4. The RavenMPIC, when present, should be used for these interrupts. ISA DMA Channels The MVME2300 series boards do not implement any ISA DMA channels. http://www.motorola.com/computer/literature ISA DMA Channels...
Page 252: Exceptions
Programming Details Exceptions Sources of Reset There are eight potential sources of reset on MVME2300 series boards. They are: 1. Power-On reset 2. RESET switch 3. Watchdog Timer reset via the MK48T59/559 Timekeeper device 4. Port 92 Register via the PIB 5.
Page 253: Table 5-4. Reset Sources And Devices Affected
Processor Init register of the RavenMPIC appropriately. Universe Chip Problems after PCI Reset Under certain conditions, there may be problems with the Universe chip after a PCI reset. Refer to Chapter 4 for details. http://www.motorola.com/computer/literature Universe Chip Problems after PCI Reset Exceptions...
Page 254: Table 5-5. Error Notification And Handling
RavenMPIC interrupts or Machine Check Interrupt. Note that the TEA signal is not used at all by the MVME2300 series. The following table summarizes how hardware errors are handled by the MVME2300 series boards: Table 5-5.
Page 255: Figure 5-3. Big-Endian Mode
Because the PowerPC processor is inherently big-endian, PCI is inherently little-endian, and the VMEbus is big-endian, there is potential for confusion. The figures below illustrate how the MVME2300 series boards handle the endian issue in big-endian and little-endian modes.
Page 256: Figure 5-4. Little-Endian Mode
Programming Details Little-Endian PROGRAM EA Modification (XOR) Raven Universe N-way Byte Swap 5-12 60X System Bus EA Modification PCI Local Bus VMEbus Figure 5-4. Little-Endian Mode Computer Group Literature Center Web Site Little-Endian Big-Endian Falcons DRAM Big-Endian Little-Endian Little-Endian Big-Endian 1899 9609...
Page 257: Processor/Memory Domain
PCI will operate in little-endian mode, regardless of the mode of operation in the processor’s domain. PCI-SCSI The MVME2300 series boards do not implement SCSI. PCI/Ethernet Ethernet is byte-stream-oriented, with the byte having the lowest address in memory being the first one transferred regardless of endian mode. Since address invariance is maintained by the Raven in both little-endian and http://www.motorola.com/computer/literature...
Page 258: Pci-Graphics
VMEbus are expected to operate in big-endian mode, regardless of the mode of operation in the processor’s domain. In big-endian mode on the MVME2300 series boards, byte swapping is performed by the Universe and then by the Raven. The result has the desirable effect of being transparent to the big-endian software.
Page 259: Rom/Flash Initialization
Software can determine the mapping of the FFF00000-FFFFFFFF address range by examining the rom_b_rv bit in the Falcon’s Rom B Base/Size register. Table 5-6. ROM/Flash Bank Default rom_b_rv http://www.motorola.com/computer/literature Default Mapping for FFF00000-FFFFFFFF ROM/FLASH Bank A ROM/FLASH Bank B ROM/Flash Initialization...
Page 261: Motorola Computer Group Documents
ARelated Documentation Motorola Computer Group Documents The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by: Contacting your local Motorola sales office Visiting MCG’s World Wide Web literature site, http://www.motorola.com/computer/literature...
Page 262: Manufacturers' Documents
® PowerPC 603e RISC Microprocessor Technical Summary ® PowerPC 604e RISC Microprocessor Technical Summary Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 WebSite: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com ® PowerPC 603e RISC Microprocessor User’s Manual ®...
Page 263 Document Title and Source ® PowerPC Microprocessor Family: The Programming Environments for 32-Bit Microprocessors Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 WebSite: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com IBM Microelectronics Programming Environment Manual Web Site: http://www.chips.ibm.com/techlib/products/powerpc/manuals...
Page 264: Related Specifications
Related Documentation Related Specifications For additional information, refer to the following table for related specifications. For your convenience, a source for the listed document is also provided. It is important to note that in many cases, the information is preliminary and the revision levels of the documents are subject to change without notice.
Page 265 Third Edition, Version 1.0, Volumes I and II International Business Machines Corporation Web Site: http://www.ibm.com PowerPC Microprocessor Common Hardware Reference Platform: A System Architecture (CHRP), Version 1.0 Literature Distribution Center for Motorola Telephone: 1-800- 441-2447 FAX: (602) 994-6430 or (303) 675-2150 Web Site: http://e-www.motorola.com/webapp/DesignCenter/ E-mail: ldcformotorola@hibbertco.com Morgan Kaufmann Publishers, Inc.
Page 267 An Ethernet implementation in which the physical medium is a 10Base-5 doubly shielded, 50-ohm coaxial cable capable of carrying data at 10 Mbps for a length of 500 meters (also referred to as thicknet). Also known as thick Ethernet. An Ethernet implementation in which the physical medium is a 10Base-2 single-shielded, 50-ohm RG58A/U coaxial cable capable of carrying data at 10 Mbps for a length of 185 meters (also referred to...
Page 268 big-endian cache CISC DIMM DRAM EEPROM GL-2 A byte-ordering method in memory where the address n of a word corresponds to the most significant byte. In an addressed memory word, the bytes are ordered (left to right) 0, 1, 2, 3, with 0 being the most significant byte.
Page 269 Ethernet carried by coaxial cables. Falcon The DRAM controller chip developed by Motorola for the MVME2600 and MVME3600 series of boards. It is intended to be used in sets of two to provide the necessary interface between the Power PC60x bus and the 144-bit ECC DRAM (system memory array) and/or ROM/Flash.
Page 270 In an addressed memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3 being the most significant byte. Motorola’s component designations for the PowerPC 603 and PowerPC 604 microprocessors. Multi-Processor Interrupt Controller...
Page 271 Instructions can be sent simultaneously to three types of independent execution units (branch units, fixed-point units, and floating-point units), where they can execute concurrently, but finish out of order. PowerPC is used by Motorola, Inc. under license from IBM. Random-Access Memory. The temporary memory that a computer uses to hold the instructions and data currently being worked with.
Page 272 SCSA SCSI SCSI-2 (Fast/Wide) serial port SIMM software SRAM thick Ethernet GL-6 Signal Computing System Architecture. A hardware model for computer telephony servers. A key SCSA element is a TDM (time division multiplexed) telephony bus for voice and video signals, known as the SCbus™...
Page 273 See 10Base-T. twisted-pair Ethernet Universal Asynchronous Receiver/Transmitter UART Universe ASIC developed by Tundra in consultation with Motorola which provides the complete interface between the PCI bus and the VMEbus. VESA (bus) Video Electronics Standards Association (or VL bus). An internal interconnect standard for transferring video information to a computer display system.
Page 275 Raven PCI Bridge ASIC binary number, symbol for bit ordering conventions (Falcon chip set) block diagrams Falcon ECC Memory Controller chip set MVME2300 series boards PIB interrupt handler Raven interrupt controller function Raven PCI Bridge ASIC 3-17 board connectors...
Page 276 CONFIG_DATA register configuration registers (Raven PCI Bridge ASIC) 2-11 connectors, MVME2300 series boards control bit, definition of control registers, writing to (Falcon chip set) 3-53 control/status registers (Falcon chip set) CPU Configuration register CPU Control register 1-30 CSR accesses (Falcon chip set)
Page 277 (Falcon chip set) Feature Reporting register (RavenMPIC) 2-73 features Falcon ECC Memory Controller chip set MVME2300 series boards Raven PCI Bridge ASIC Universe ASIC 4-1, Flash (see ROM/Flash interface) 3-14 functional description Falcon ECC Memory Controller chip set...
Page 278 Slave Offset/Attribute (0,1 and 2) regis- Slave Offset/Attribute (3) registers write posting (Raven PCI Bridge ASIC) MPC-to-PCI address decoding MPC-to-PCI address translation MPIC registers (Raven ASIC) MVME2300 series interrupt architecture negation, definition of NVRAM/RTC 2-48 2-49 P2 signal routing parity checking and Falcon chip set...
Page 279 CHRP memory map Processor Init register (RavenMPIC) processor memory maps processor PREP memory map 1-11 programming details programming model Falcon chip set 3-21 MVME2300 series boards programming notes 2-87 programming ROM/Flash 3-53 program-visible registers (Raven interrupt controller) 2-66 Raven interrupt controller implementation...
Page 280 LM/SIG Status 1-39 Location Monitor Lower Base Address 1-41 Location Monitor Upper Base Address 1-41 Memory Configuration (MEMCR) MK48T59/559 access module configuration and status NVRAM/RTC and Watchdog Timer 1-32 Raven configuration Raven MPC 1-10, RavenMPIC control Semaphore Register 1 Semaphore Register 2 System Configuration (SYSCR) System External Cache Control (SXC- 1-29...
Page 281 Revision ID/Class Code registers (Raven ASIC) 2-52 Revision ID/General Control register (Falcon chip set) 3-31 5-15 ROM/Flash initialization 5-15 http://www.motorola.com/computer/literature 2-54 interface (Falcon chip set) programming speed 3-10 ROM/FLASH bank default mapping ROM/Flash Block A Base Address control bits (Falcon chip set)
Page 282 status bit, definition of symbols, use of xxii syndrome codes, ECC (Falcon chip set) System Configuration register (SYSCR) System External Cache Control register (SX- CCR) 1-29 Timer registers (Raven MPIC) Base Count registers Current Count registers Destination registers Frequency register Vector/Priority registers timing (DRAM access) 3-7, 3-8, timing (ROM/Flash access)

Motorola MVME2300 Series Programmer's Reference Manual

About this Manual

CHAPTER 1 Board Description and Memory Maps

CHAPTER 2 Raven PCI Bridge ASIC

CHAPTER 3 Falcon ECC Memory Controller Chip Set

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Summary of Contents for Motorola MVME2300 Series