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Universe (VMEbus to PCI) Chip
4
Universe Control and Status Registers (UCSR)
4-8
Following specific rules of DMAFIFO operation (refer to FIFO Operation
and Bus Ownership in the Universe User Manual), it then acquires the
destination bus and writes data from its DMAFIFO.
The DMA controller can be programmed to perform multiple blocks of
transfers using entries in a linked list. The DMA will work through the
transfers in the linked-list following pointers at the end of each linked-list
entry. Linked-list operation is initiated through a pointer in an internal
Universe register, but the linked list itself resides in PCI bus memory.
The Universe Control and Status Registers (UCSR) facilitate host system
configuration and allow the user to control Universe operational
characteristics. The UCSR set is divided into three groups:
PCI Configuration Space (PCICS)
VMEbus Control and Status Registers (VCSR)
Universe Device-Specific Status Registers (UDSR)
The Universe registers are little-endian.
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