QQ
3 7 63 1515 0
Pin No.
Pin Name
113
114
VDDINT
115
116
VDDEXT
117
118
VDDINT
119
120
VDDINT
121
122
123
124
VDDINT
125
126
127
128
129
VDDINT
130
VDDEXT
131
TE
132
L 13942296513
133
134
CLKOUT
135
136
137
138
139
140
141
142
143
144
VDDEXT
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I/O
GND
—
Ground terminal
—
Power supply terminal (+1.2V) (for core)
GND
—
Ground terminal
—
Power supply terminal (+3.3V) (for I/O)
GND
—
Ground terminal
—
Power supply terminal (+1.2V) (for core)
GND
—
Ground terminal
—
Power supply terminal (+1.2V) (for core)
RESET
I
Reset signal input from the system controller "L": reset
SPIDS
I
Device selection signal input from the system controller
GND
—
Ground terminal
—
Power supply terminal (+1.2V) (for core)
SPICLK
I
Serial data transfer clock signal input from the system controller
When DSP is master: Serial data input from the flash memory
MISO
I/O
When DSP is slave: Serial data output to the main system controller
When DSP is master: Serial data output to the flash memory
MOSI
I/O
When DSP is slave: Serial data input from the main system controller
GND
—
Ground terminal
—
Power supply terminal (+1.2V) (for core)
—
Power supply terminal (+3.3V) (for I/O)
AVDD
—
Power supply terminal (+1.2V) (analog system)
AVSS
—
Ground terminal (analog system)
GND
—
Ground terminal
O
Not used (Open)
EMU*
O
Not used (Open)
TDO
O
Not used (Open)
TDI
I
Not used (Fixed to "L")
TRST*
I
Not used (Fixed to "L")
TCK
I
Not used (Fixed to "L")
TMS
I
Not used (Fixed to "L")
GND
—
Ground terminal
CLKIN
I
System clock input terminal (25 MHz)
XTAL
O
System clock output terminal (25 MHz)
—
Power supply terminal (+3.3V) (for I/O)
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8
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u163
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HCD-DZ830W/DZ850KW
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
89