Sony MDX-C8900R Service Manual page 67

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Pin No. Pin Name
68 SUBCE
69
FLASH-W
70 RDSSI
71 RDSCKO
72 RC-IN1
73 X1A
74 X0A
75 DAVN
76 KEYACK
77 BU-IN
78 ILL IN
79 TEL-ATT
80 NOSESW
81 ACC IN
82 to 85
TIR-D0 to TIR-D3
86 HSTX
87 MD2
TE
L 13942296513
88 MD1
89 MD0
90 RESET
91 VSS
92 X0
93 X1
94 VCC
95 TIR-BUSY
96 TIR-WR
97 TIR-CE
98 TIR-CE
99 TIR-RES
100 TIR-PDOWN
101 TIR-RD
102 MTLIN
103 AM STIN
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104 LOCK
105 to108 POS0 to POS3
.
109 MD-ATT
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I/O
O Chip enable signal output to the sub electrical volume (IC403) "H" active
Internal flash memory data write mode detection signal input terminal "L": data write mode
I
Not used (fixed at "H" in this set)
I
Serial data input from the RDS decoder (IC701)
O Serial data reading clock signal output to the RDS decoder (IC701)
I Rotary remote commander shift key input terminal "L": shift
O
Sub system clock output terminal (32 kHz)
I
Sub system clock input terminal (32 kHz)
I Data transmit completed detect signal input from the RDS decoder (IC701) "H" active
Input of acknowledge signal for the key entry Acknowledge signal is input to accept function
I
and eject keys in the power off status On at input of "H"
Battery detect signal input from the SONY bus interface (IC504) and battery detect circuit
I
"L" is input at low voltage
Auto dimmer control illumination line detection signal input terminal
I
"L" is input at dimmer detection
I Telephone muting signal input terminal At input of "L", the signal is attenuated by –20 dB
Front panel block remove/attach detection switch (SW503) signal input terminal
I
"L": front panel is attached
I Accessory detect signal input terminal "L": accessory on
I/O
Two-way data bus with the MSM6688GS (IC703)
I
Hardware standby input terminal "L": hardware standby mode Reset signal input in this set
I
Setting terminal for the CPU operational mode (fixed at "L" in this set)
I
Setting terminal for the CPU operational mode (fixed at "H" in this set)
I
Setting terminal for the CPU operational mode (fixed at "H" in this set)
System reset signal input from the reset signal generator (IC505) and reset switch (SW701)
I
"L" is input for several 100 msec after power on, then it changes to "H"
—
Ground terminal
I Main system clock input terminal (3.68 MHz)
O Main system clock output terminal (3.68 MHz)
—
Power supply terminal (+5V)
Busy detection signal input from the MSM6688GS (IC703)
I
"H" is output while MSM6688GS (IC703) is executing a command
Data write strobe signal output to the MSM6688GS (IC703)
O
"L" is output when data (D0 to D3) are output to the MSM6688GS (IC703)
O
Chip enable signal output to the MSM6688GS (IC703)
TIR-WR (pin (§) or TIR-RD (pin `⁄‚⁄) is accepted when CE is "L" or CE is "H" respectively
TIR-WR (pin (§) or TIR-RD (pin `⁄‚⁄) is not accepted when CE is "H" or CE is "L" respectively
O
O
Reset signal output to the MSM6688GS (IC703) "H": reset
O
Power down control signal output to the MSM6688GS (IC703) "L": power down
Data read strobe signal output to the MSM6688GS (IC703)
O
"L" is output when data (D0 to D3) are output to the MSM6688GS (IC703)
I
Not used (fixed at "L")
I Not used (fixed at "L")
Mini-disc lock detection signal input from the MD mechanism controller (IC501) "H": lock
I
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CLV lock status input in test mode
I Not used (fixed at "L")
i
The audio muting control signal is input from the MD mechanism controller (IC501), and output
I
to ATT (pin ^∞)
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8
Function
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