Sony MDX-C8900R Service Manual page 60

QQ
3 7 63 1515 0
– AUDIO Board –
IC901 RSC-164
48
BUFFER
DAC ANALOG
CONTROL
ADC
SH 49
AIN1 50
ADC
MUX
AIN0 51
AGND 52
BUFOUT/PWM0 53
54
TEST/PWM1
AVDD 55
GND 56
D7
57
D6 58
D5
59
D4 60
D3 61
D2
62
D1 63
D0
64
TE
L 13942296513
1
IC902 MBM29F800TA
A15
1
A14
2
A13
3
X
A12
4
DECODER
A11
5
A10
6
A9
7
ADDRESS
A8
LATCH
8
Y
DECODER
9 NC
10 NC
STB
WE CONTROL
11
CIRCUIT
RESET
12
13 NC
14 NC
RY/BY
15
www
A18
16
A17
17
A7
18
RY/BY
A6
BUFFER
19
A5
20
.
A4
21
OUTPUT ENABLE
A3
22
A2
23
A1
24
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47 46 45 44 43 42 41 40
INTERNAL ROM
32 X 8 (HIGH)
INTERNAL ROM
32 X 8 (LOW)
INTERNAL BUS
INTERRUPT
EXTERNAL MEMORY
INTERFACE
POWER
CONTROL
WAKEUP LOGIC
(FROM PORT 0/1)
ADDRESS BUS
2 3 4 5 6 7 8 9 10 11 12 13 14 15
8,388,608
CELL
MATRIX
Y GATE
I/O
BUFFER
DATA
LATCH
STB
LOW VCC
DETECTOR CIRCUIT
WRITE/ERASE
PULSE TIMER
WRITE CIRCUIT
x ao
y
ERASE CIRCUIT
i
CHIP ENABLE/
CIRCUIT
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8
39 38 37 36 35 34 33
PORT 0
REGISTER STACK
CPU
SPACE SPACE
PULSE WIDTH
MODULATOR
LOGIC
TIMING &
TIMER
CONTROL
Q Q
3 6 7 1 3
16
IC903 MSM534001E-14TSKFDR3
A16
48
BYTE
47
GND 46
DQ15/A–1
45
DQ7
44
DQ14
43
DQ6
42
DQ13
41
DQ5
40
DQ12
39
DQ4
38
VCC 37
DQ11
36
DQ3
35
DQ10
34
DQ2
33
DQ9
32
DQ1
31
DQ8
30
DQ0
29
u163
OE
28
.
GND 27
CE
26
A0
25
– 80 –
2 9 9 4 2 8
32 P07
31 P10
30 P11
P12
29
28 P13
27 P14
26 P15
25 P16
24 P17
23 VDD
GND
22
21 RESET
OSC XI1
20
19 XO1
18 A0
17 A1
1 5 0 5 8 2 9 9 4
32 31 30 29 28 27 26 25 24 23 22 21 20 19
MEMORY CELL
X
MATRIX
DECODER
524,288 X 8
ADDRESS
BUFFER
Y
MULTIPLEXER
DECODER
CE/OE
OUTPUT
CONTROL
BUFFER
1 2 3 4 5 6 7 8 9 10 11 12 13 14
m
co
9 9
2 8 9 9
18 17
15 16