Pll Frequency Synthesizer; Control Circuit; Pll Circuit/Unlock Circuit; Vco Circuit - Kenwood TK-7360 Service Manual

4. PLL Frequency Synthesizer

The PLL circuit generates the fi rst local oscillator signal
for reception and the RF signal for transmission.
4-1. PLL Circuit
The frequency step of the PLL circuit is 5, 6.25, 7.5, 10,
12.5 or 15kHz.
A 19.2MHz reference oscillator signal is divided at IC2
by a fi xed counter to produce the reference frequency. The
voltage controlled oscillator (VCO) output signal is buffer
amplifi ed by Q12, then multiplied by using a doubler and di-
vided by a programmable counter in IC2.
The divided signal is compared in phase with the refer-
ence signal in the phase comparator in IC2. The output
signal from the phase comparator is fi ltered through a low-
IC2: PLL IC
1/N
PLL
DATA comparator
REF
OSC
1/M
19.2MHz
4-3. Unlock Circuit
During reception, the 9RC signal goes high, the 9TC sig-
nal goes low, and Q400 turns on. Q402 turns on and a volt-
age is applied to the collector (9R). During transmission, the
9RC signal goes low, the 9TC signal goes high and Q401
turns on. Q403 turns on and a voltage is applied to 9T.
The MCU in the control unit monitors the PLL (IC2) LD
signal directly. When the PLL is unlocked during transmis-
sion, the PLL LD signal goes low. The MCU detects this
signal and makes the 9TC signal low. When the 9TC signal
goes low, no voltage is applied to 9T, and no signal is trans-
mitted.
Q402
9R
SW
Q400
SW
9RC
IC704
MCU
Fig. 9 Unlock circuit
CIRCUIT DESCRIPTION
Phase Charge
pump
IC3
OP
ASTC
AMP
Fig. 8 PLL circuit
9C
Q403
9T
SW
Q401
SW
9TC
LD
IC2
PLL
PLL lock
: LD "H"
TK-7360/7360H/7360H
pass fi lter and passed to the VCO to control the oscillator
frequency.

4-2. VCO Circuit

The operating frequency is generated by Q6 in transmit
mode and Q8 in receive mode. The oscillator frequency is
controlled by applying the VCO control voltage, obtained
from the phase comparator to the varactor diodes (D6 and
D7 in transmit mode and D8 and D9 in receive mode) and
assist voltage to the (D10, D12 and D13 in transmit mode
and D11, D14 and D15 in receive mode).
The TX/RX pin is set high in receive mode causing Q7 to
turn off, and turn Q10 on. The TX/RX pin is set low in trans-
mit mode. The outputs from Q8 and Q6 are amplified by
Q12 and sent to the RF amplifi ers.
D10,D12,D13
LPF
D6,D7
D8,D9
Assist
voltage
D11,D14,D15

5. Control Circuit

The MCU carries out the following tasks:
1) Controls the WIDE, NARROW, TX/RX outputs.
2) Controls the Baseband IC (IC702).
3) Controls the PLL (IC2).
4) Controls the display unit.
BLED
GLED
RLED
MBL
BLC
Display unit
Fig. 10 Control circuit
Q3
Q6
Doubler
TX VCO
AMP
Q12
BUFF
AMP
Q8
RX VCO
Q7,Q10
T/R SW
IC2
PLL
CDATA
SCLK
RDATA
IC704 IC702
MCU Baseband IC
IRQ
CSN
IC1
LCD driver
V
( )
15