MSI K7N2M Manual page 56

BIOS Setup
FSB/DRAM Ratio
This setting controls the ratio of CPU FSB clock & DRAM Frequency to
enable the CPU & DRAM to run at different frequency combinations. Please
note that the setting options vary according to the CPU FSB clock preset.
Options: By SPD, 2:1, 5:3, 3:2, 4:3, 5:4, 6:5, 1:1, 5:6, 4:5, 3:4, 2:3, 3:5, 1:2.
Current DRAM Clock
It shows the clock frequency of the installed DRAMs. (read only)
Memory Timings
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to By SPD enables DRAM
timings to be determined by BIOS based on the configurations on the SPD.
Selecting Manual allows users to configure the DRAM timings manually.
Options: By SPD, Manual, High Performance.
T-(RAS)
This setting controls the number of clock cycles for DRAM to be allowed to
precharge from the active state. Settings: 1 through 15.
T-(RCD)
When DRAM is refreshed, both rows and columns are addressed separately.
This setup item allows you to determine the timing of the transition from RAS
(row address strobe) to CAS (column address strobe). The less the clock
cycles, the faster the DRAM performance. Setting options: 1 through 7.
T-(RP)
This item controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If insufficient time is allowed for the RAS to accumu-
late its charge before DRAM refresh, refresh may be incomplete and DRAM
may fail to retain data. This item applies only when synchronous DRAM is
installed in the system. Available settings: 1 through 7.
CAS Latency
The fid controls the CAS latency, which determines the timing delay before
RAM starts a read command after receiving it. Setting options are: 2, 2.5, and
3. 2T increases system performance while 3T provdes more stable system
performance.
3-13