Burst Cycles - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
SIZ[1:0], TT[1:0]
SIZ[1:0], TT[1:0]

2.1.3 Burst Cycles

Interfacing to the Motorola MCF5307 "ColdFire" Microprocessor
Issue Date: 01/02/23
Figure 2-1: "MCF5307 Memory Read Cycle," illustrates a typical memory read cycle on
the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start Wait States
Figure 2-1: MCF5307 Memory Read Cycle
Figure 2-2: "MCF5307 Memory Write Cycle," illustrates a typical memory write cycle on
the MCF5307 system bus.
BCLK0
TS
TA
TIP
A[31:0]
R/W
D[31:0]
Transfer Start
Figure 2-2: MCF5307 Memory Write Cycle
Burst cycles are very similar to normal cycles, except that they occur as a series of four
back-to-back, 32-bit memory reads or writes. The TIP (Transfer In Progress) output is
asserted continuously through the burst. Burst memory cycles are mainly intended to fill
Transfer
Complete
Valid
Wait States Transfer
Complete
Sampled when TA low
Next Transfer
Starts
Next Transfer
Starts
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S1D13706
X31B-G-010-02