Table 8-19: Pwmout Duty Cycle Select Options - Epson S1D13706 Technical Manual

Epson Research and Development
Vancouver Design Center
CV Pulse Burst Length Register
REG[B2h]
7 6
bits 7-0
PWMOUT Duty Cycle Register
REG[B3h]
7 6
bits 7-0
PWMOUT Duty Cycle [7:0]
Hardware Functional Specification
Issue Date: 01/11/13
CV Pulse Burst Length Bits 7-0
5
CV Pulse Burst Length Bits [7:0]
The value of this register determines the number of pulses generated in a single CV Pulse
burst:
Number of pulses in a burst = (ContentsOfThisRegister) + 1
PWMOUT Duty Cycle Bits 7-0
5
PWMOUT Duty Cycle Bits [7:0]
This register determines the duty cycle of the PWMOUT output.

Table 8-19: PWMOUT Duty Cycle Select Options

00h
01h
02h
...
FFh
4 3
4 3
PWMOUT Duty Cycle
High for 1 out of 256 clock periods
High for 2 out of 256 clock periods
High for 255 out of 256 clock periods
2 1
2 1
Always Low
...
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Read/Write
0
Read/Write
0
S1D13706
X31B-A-001-08