Tektronix GTS1250 Manuals

Manuals and User Guides for Tektronix GTS1250. We have 1 Tektronix GTS1250 manual available for free PDF download: Instruction Manual

Tektronix GTS1063 Instruction Manual

Tektronix GTS1250 Instruction Manual (120 pages)

GBIC Test Systems

Brand: Tektronix | Category: Test Equipment | Size: 3.74 MB

Table of Contents
6
List of Figures
8
Figure 25: Random Jitter Histogram
9
List of Tables
10
General Safety Summary
12
Service Safety Summary
14
Contacting Tektronix
16
Preface
17
Related Manuals
17
Figure 1: GTS1063 and GTS1250 Front Panels
18
Getting Started
18
Table 1: Options
20
Table 2: Standard Accessories
20
Options
20
Standard Accessories
20
Table 3: Optional Accessories
21
Optional Accessories
21
Installation
21
Figure 2: a GBIC Example
22
Figure 3: GBIC Test System with Zoomed GBIC Receptacle
23
Operating Basics
26
Handling
26
Connecting Signals
26
Figure 4: the GTS1063 and GTS1250 Front Panels
27
Front Panel
27
Figure 5: Rx_Data Min-Loss Signal, Recovered Clock, and DATA Paths
31
Figure 6: Rear Panel of GTS1250
33
Rear Panel
33
Figure 7: Rear Remote Interface Connector Pinout
34
Table 2: Remote Pattern Selection Codes
35
Figure 8: Serial ID Connections to Rear Panel and GBIC
38
Figure 9: Isometric View of AMP GBIC Receptacle Rail Guide Assembly
39
Figure 10: GBIC Pinout Supported by the GBIC Test System Receptacle
39
GBIC Receptacle
39
Table 3: GBIC Pin Assignment
40
Using the Rear Panel TTL REMOTE Interface
40
Connecting to a BERT, and Testing the Bit Error Rate
41
Figure 11: BER Test of GBE Fiber Path
42
Figure 12: BER Test of GBE Fiber Path
42
Figure 13: Stress Testing Via Increasing Transmitted Jitter through
43
Adding Jitter to the Transmitted Signal
43
Figure 14: Stress Testing Via Increasing Deterministic Jitter through
44
Fiber Path Repeater or Monitor
44
Figure 15: Using the GBIC Test System as a Fiber Path Repeater
45
Figure 17: GBIC Test System Modifications before Installation in Rack Adapter
45
Installation in a Rack
45
Table 4: Tx Data and Tx Clock out Specifications
46
Specifications
46
Table 5: External Data Input Specifications
48
Table 6: External Clock Input Specifications
48
Table 7: External Tx Jitter Input Specifications
49
Table 8: Rx Electrical Specifications
50
Table 9: Internal DC Power Supply Specifications
52
Table 10: GBIC Receptacle Supply Specifications
53
Table 11: Rear-Panel Interface Connector Level Specifications
53
Table 12: Environmental Characteristics
54
Table 13: Electromagnetic Compatibility (EMC)
56
Table 14: Safety Characteristics
56
Table 15: Certifications and Compliances
58
Performance Verification
60
Prerequisites
60
Table 16: Test Equipment
61
Equipment Required
61
GTS1250 GBIC Test System Test Record
62
Setup for PV
63
Tx DATA, CLOCK, and SYNC Output Levels
63
Figure 18: Tx Data Levels (Swing)
64
Figure 19: Tx CLK Levels
65
Figure 20: SYNC Levels
66
Recovered Data and Clock Output Levels (Option 01 Only)
67
Figure 21: Recovered Clock and Data Levels
68
Tx Data Duty Cycle
69
Figure 22: Tx Data Duty Cycle
70
Tx Clock to Data Random Jitter
71
Figure 23: Tx Clock to Data Random Jitter Test Setup
72
Figure 24: Centered Rising Edge
73
Figure 26: Tx Data Deterministic Jitter Test Setup
75
Fast Deterministic Jitter
75
Figure 27: Histogram Deterministic Jitter Measurement
77
Figure 28: Tx Data Deterministic Jitter Test Setup
78
Tx DATA to SYNC out Deterministic Jitter
78
Table 17: Deterministic Jitter Calculation
83
Table 18: Example Deterministic Jitter Calculation
83
Recovered Clock to Data Random Jitter
84
GBIC Port VDD Default Voltage
87
Table 19: Required Tools for Fuse Removal and Replacement
90
Fuse Removal and Replacement
90
Table 20: Cable Connections
93
Replaceable Parts
94
Appendix A: GTS1250 Long and Short Patterns
100
The IEEE 802.3 Patterns
100
Table 21: LONG Continuous Random Test Pattern Data Sequence
101
Table 22: SHORT Continuous Random Test Pattern Data Sequence
102
Appendix B: GTS1063 CRPAT and CJTPAT Patterns
104
Fibre Channel MJS Jitter Test Patterns
104
Table 23: CRPAT Compliant Random Pattern Data Sequence
105
Table 24: CJTPAT Compliant Jitter Tolerance Pattern Data Sequence
106
Appendix C: Recovering a Clock from an External Electrical Signal
108
Rx DATA Connectors Used as Electrical Inputs
108
Overriding RX_LOS to Enable the Clock Recovery Circuit
108
Proper AC Input Coupling: Single-Ended or Complimentary
108
Proper Internal Termination: Using a Powered down GBIC as a Termination
109
Input Sensitivity
109
Glossary
110
Index
116

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