SMSC LAN9312 Manuals

Manuals and User Guides for SMSC LAN9312. We have 1 SMSC LAN9312 manual available for free PDF download: Datasheet

SMSC LAN9312 Datasheet (458 pages)

High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface

Brand: SMSC | Category: Switch | Size: 4 MB

Product Features
1
Order Numbers
2
Table of Contents
3
Chapter 1 Preface

16
- General Terms
  16
- Buffer Types
  18
- Table 1.1 Buffer Types
  18
- Register Nomenclature
  19
- Table 1.2 Register Bit Types
  19
Chapter 2 Introduction

20
- General Description
  20
- Block Diagram
  21
- Figure 2.1 Internal LAN9312 Block Diagram
  21
- System Clocks/Reset/Pme Controller
  22
- System Interrupt Controller
  22
- Switch Fabric
  23
- Ethernet Phys
  23
- Host Bus Interface (HBI)
  23
- Host MAC
  24
- EEPROM Controller/Loader
  24
- 1588 Time Stamp
  24
- GPIO/LED Controller
  25
- System Configuration
  25
- Figure 2.2 System Block Diagram
  25
Chapter 3 Pin Description and Configuration

26
Chapter 4 Clocking, Resets, and Power Management

36
- Clocks
  36
- Resets
  36
- Chip-Level Resets
  37
- Power-On Reset (POR)
  37
- Table 4.1 Reset Sources and Affected LAN9312 Circuitry
  37
- Nrst Pin Reset
  38
- Multi-Module Resets
  38
- Digital Reset (DIGITAL_RST)
  38
- Soft Reset (SRST)
  39
- Single-Module Resets
  39
- Port 2 PHY Reset
  39
- Port 1 PHY Reset
  39
- Virtual PHY Reset
  40
- Configuration Straps
  40
  - Soft-Straps
    40
  - Table 4.2 Soft-Strap Configuration Strap Definitions
    41
- Hard-Straps
  45
- Power Management
  46
- Table 4.3 Hard-Strap Configuration Strap Definitions
  46
- Port 1 & 2 PHY Power Management
  47
- Figure 4.1 PME and PME_INT Signal Generation
  47
- Host MAC Power Management
  48
Chapter 5 System Interrupts

49
- Functional Overview
  49
- Interrupt Sources
  49
- Figure 5.1 Functional Interrupt Register Hierarchy
  50
- 1588 Time Stamp Interrupts
  51
- Switch Fabric Interrupts
  51
- Ethernet PHY Interrupts
  52
- GPIO Interrupts
  52
- Host MAC Interrupts
  52
- Power Management Interrupts
  53
- General Purpose Timer Interrupt
  53
- Software Interrupt
  54
- Device Ready Interrupt
  54
Chapter 6 Switch Fabric

55
- Functional Overview
  55
- Switch Fabric Csrs
  55
- Switch Fabric CSR Writes
  56
- Switch Fabric CSR Reads
  57
- Figure 6.1 Switch Fabric CSR Write Access Flow Diagram
  57
- Flow Control Enable Logic
  58
- Figure 6.2 Switch Fabric CSR Read Access Flow Diagram
  58
- Table 6.1 Switch Fabric Flow Control Enable Logic
  59
- 10/100 Ethernet Macs
  60
- Receive MAC
  60
- Receive Counters
  61
- Transmit MAC
  62
- Transmit Counters
  62
- Switch Engine (SWE)
  63
- MAC Address Lookup Table
  63
- Figure 6.3 ALR Table Entry Structure
  63
- Learning/Aging/Migration
  64
- Static Entries
  64
- Multicast Pruning
  64
- Address Filtering
  64
- Spanning Tree Port State Override
  64
- MAC Destination Address Lookup Priority
  64
- Host Access
  64
- Forwarding Rules
  66
- Transmit Priority Queue Selection
  67
- Figure 6.4 Switch Engine Transmit Queue Selection
  67
- Figure 6.5 Switch Engine Transmit Queue Calculation
  68
- Port Default Priority
  69
- IP Precedence Based Priority
  69
- DIFFSERV Based Priority
  69
- VLAN Priority
  69
- VLAN Support
  70
- Spanning Tree Support
  70
- Figure 6.6 VLAN Table Entry Structure
  70
- Table 6.2 Spanning Tree States
  70
- Ingress Flow Metering and Coloring
  71
- Ingress Flow Calculation
  72
- Table 6.3 Typical Ingress Rate Settings
  72
- Figure 6.7 Switch Engine Ingress Flow Priority Selection
  73
- Figure 6.8 Switch Engine Ingress Flow Priority Calculation
  73
- Broadcast Storm Control
  74
- Ipv4 IGMP / Ipv6 MLD Support
  74
- Table 6.4 Typical Broadcast Rate Settings
  74
- Port Mirroring
  75
- Host CPU Port Special Tagging
  75
- Packets from the Host CPU
  75
- Packets to the Host CPU
  76
- Counters
  76
- Buffer Manager (BM)
  77
- Packet Buffer Allocation
  77
- Buffer Limits and Flow Control Levels
  77
- Random Early Discard (RED)
  77
- Transmit Queues
  77
- Transmit Priority Queue Servicing
  78
- Egress Rate Limiting (Leaky Bucket)
  78
- Table 6.5 Typical Egress Rate Settings
  78
- Adding, Removing, and Changing VLAN Tags
  79
- Figure 6.9 Hybrid Port Tagging and Un-Tagging
  80
- Counters
  81
- Switch Fabric Interrupts
  81
Chapter 7 Ethernet Phys

82
- Functional Overview
  82
- PHY Addressing
  82
- Table 7.1 Default PHY Serial MII Addressing
  82
- Port 1 & 2 Phys
  83
- Figure 7.1 Port X PHY Block Diagram
  83
- 100BASE-TX Transmit
  84
- MII MAC Interface
  84
- 5B Encoder
  84
- Figure 7.2 100BASE-TX Transmit Data Path
  84
- Table 7.2 4B/5B Code Table
  85
- Scrambler and PISO
  86
- NRZI and MLT-3 Encoding
  86
- Transmit Driver
  86
- Phase Lock Loop (PLL)
  86
- 100BASE-TX Receive
  87
- A/D Converter
  87
- DSP: Equalizer, BLW Correction and Clock/Data Recovery
  87
- Figure 7.3 100BASE-TX Receive Data Path
  87
- NRZI and MLT-3 Decoding
  88
- Descrambler and SIPO
  88
- 4B Decoding
  88
- Receiver Errors
  88
- MII MAC Interface
  88
- 10BASE-T Transmit
  89
- MII MAC Interface
  89
- 10M TX Driver and PLL
  89
- 10BASE-T Receive
  89
- Filter and Squelch
  89
- 10M RX and PLL
  89
- MII MAC Interface
  90
- Jabber Detection
  90
- PHY Auto-Negotiation
  90
- PHY Pause Flow Control
  92
- Parallel Detection
  92
- Restarting Auto-Negotiation
  92
- Disabling Auto-Negotiation
  92
- Half Vs. Full-Duplex
  93
- HP Auto-MDIX
  93
- MII MAC Interface
  93
- Figure 7.4 Direct Cable Connection Vs. Cross-Over Cable Connection
  93
- PHY Management Control
  94
- PHY Interrupts
  94
- PHY Power-Down Modes
  94
- Table 7.3 PHY Interrupt Sources
  94
- PHY General Power-Down
  95
- PHY Energy Detect Power-Down
  95
- PHY Resets
  95
- PHY Software Reset Via RESET_CTL
  95
  - PHY Software Reset Via Phy_Basic_Ctrl_X
    96
- PHY Power-Down Reset
  96
- Leds
  96
- Required Ethernet Magnetics
  96
- Virtual PHY
  96
- Virtual PHY Auto-Negotiation
  96
- Parallel Detection
  97
- Disabling Auto-Negotiation
  97
- Virtual PHY Pause Flow Control
  98
- Virtual PHY Resets
  98
- Virtual PHY Software Reset Via RESET_CTL
  98
- Virtual PHY Software Reset Via VPHY_BASIC_CTRL
  98
- Virtual PHY Software Reset Via PMT_CTRL
  98
Chapter 8 Host Bus Interface (HBI)

99
Chapter 9 Host MAC

112
- Functional Overview
  112
- SMSC LAN9312 5 Revision
  112
- Flow Control
  113
- Full-Duplex Flow Control
  113
- Half-Duplex Flow Control (Backpressure)
  113
- Virtual Local Area Network (VLAN) Support
  113
- Address Filtering
  114
- Figure 9.1 VLAN Frame
  114
- Perfect Filtering
  115
- Hash Only Filtering
  115
- Hash Perfect Filtering
  115
- Table 9.1 Address Filtering Modes
  115
- Inverse Filtering
  116
- Wake-Up Frame Detection
  116
- Table 9.2 Wake-Up Frame Filter Register Structure
  117
- Table 9.3 Filter I Byte Mask Bit Definitions
  117
- Table 9.4 Filter I Command Bit Definitions
  117
- Magic Packet Detection
  118
- Table 9.5 Filter I Offset Bit Definitions
  118
- Table 9.6 Filter I CRC-16 Bit Definitions
  118
- Host MAC Address
  119
- Table 9.7 EEPROM Byte Ordering and Register Correlation
  119
- Fifos
  120
- TX/RX Fifos
  120
- MIL Fifos
  120
- Figure 9.2 Example EEPROM MAC Address Setup
  120
- FIFO Memory Allocation Configuration
  121
- Table 9.8 TX/RX FIFO Configurable Sizes
  121
- TX Data Path Operation
  122
- Table 9.9 Valid TX/RX FIFO Allocations
  122
- Figure 9.3 Simplified Host TX Flow Diagram
  123
- TX Buffer Format
  124
- TX Command Format
  124
- Figure 9.4 TX Buffer Format
  124
- TX Command 'A
  125
- Table 9.10 TX Command 'A' Format
  125
- TX Command 'B
  126
- TX Data Format
  126
- TX Buffer Fragmentation Rules
  126
- Table 9.11 TX Command 'B' Format
  126
- Table 9.12 TX DATA Start Offset
  126
- Calculating Worst-Case TX MIL FIFO Usage
  127
- TX Status Format
  127
- Calculating Actual TX Data FIFO Usage
  128
- Transmit Examples
  128
- TX Example 1
  128
- Figure 9.5 TX Example 1
  129
- TX Example 2
  130
- Figure 9.6 TX Example 2
  130
- Transmitter Errors
  131
- Stopping and Starting the Transmitter
  131
- RX Data Path Operation
  132
- RX Slave PIO Operation
  132
- Figure 9.7 Host Receive Routine Using Interrupts
  133
- Figure 9.8 Host Receive Routine Using Polling
  133
- Receive Data FIFO Fast Forward
  134
- Force Receiver Discard (Receiver Dump)
  134
- RX Packet Format
  134
- RX Status Format
  135
- Figure 9.9 RX Packet Format
  135
- Stopping and Starting the Receiver
  136
- Receiver Errors
  136
Chapter 10 Serial Management

137
- Functional Overview
  137
- I2C/Microwire Master EEPROM Controller
  137
- Table 10.1 I2C/Microwire Master Serial Management Pins Characteristics
  137
- EEPROM Controller Operation
  138
- I2C Eeprom
  139
- Figure 10.1 EEPROM Access Flow Diagram
  139
- I2C Protocol Overview
  140
- Table 10.2 I2C EEPROM Size Ranges
  140
- I2C EEPROM Device Addressing
  141
- Figure 10.2 I2C Cycle
  141
- Figure 10.3 I2C EEPROM Addressing
  141
- I2C EEPROM Byte Read
  142
- I2C EEPROM Sequential Byte Reads
  142
- Figure 10.4 I2C EEPROM Byte Read
  142
- Figure 10.5 I2C EEPROM Sequential Byte Reads
  142
- I2C EEPROM Byte Writes
  143
- Figure 10.6 I2C EEPROM Byte Write
  143
- Microwire EEPROM
  144
- Microwire Master Commands
  144
- Table 10.3 Microwire EEPROM Size Ranges
  144
- Table 10.4 Microwire Command Set for 7 Address Bits
  144
- Table 10.5 Microwire Command Set for 9 Address Bits
  144
- ERASE (Erase Location)
  145
- Figure 10.7 EEPROM ERASE Cycle
  145
- Table 10.6 Microwire Command Set for 11 Address Bits
  145
- ERAL (Erase All)
  146
- EWDS (Erase/Write Disable)
  146
- Figure 10.8 EEPROM ERAL Cycle
  146
- Figure 10.9 EEPROM EWDS Cycle
  146
- EWEN (Erase/Write Enable)
  147
- READ (Read Location)
  147
- Figure 10.10EEPROM EWEN Cycle
  147
- Figure 10.11EEPROM READ Cycle
  147
- WRITE (Write Location)
  148
- WRAL (Write All)
  148
- Figure 10.12EEPROM WRITE Cycle
  148
- Figure 10.13EEPROM WRAL Cycle
  148
- EEPROM Loader
  149
- EEPROM Loader Operation
  149
- Table 10.7 EEPROM Contents Format Overview
  149
- Figure 10.14EEPROM Loader Flow Diagram
  150
- EEPROM Valid Flag
  151
- MAC Address
  151
- 3.1Host MAC Address Reload
  151
- Soft-Straps
  151
- 4.1PHY Registers Synchronization
  151
- Table 10.8 EEPROM Configuration Bits
  151
- 4.2Virtual PHY Registers Synchronization
  152
- 4.3LED and Manual Flow Control Register Synchronization
  152
- Register Data
  152
- EEPROM Loader Finished Wait-State
  153
- Reset Sequence and EEPROM Loader
  153
Chapter 11 IEEE 1588 Hardware Time Stamp Unit

154
- Functional Overview
  154
- Ieee 1588
  154
- Block Diagram
  155
- Figure 11.1 IEEE 1588 Block Diagram
  155
- IEEE 1588 Time Stamp
  156
- Figure 11.2 IEEE 1588 Message Time Stamp Point
  156
- Table 11.1 IEEE 1588 Message Type Detection
  156
- Capture Locking
  157
- Table 11.2 Time Stamp Capture Delay
  157
- PTP Message Detection
  158
- Table 11.3 PTP Multicast Addresses
  158
- IEEE 1588 Clock
  159
- Table 11.4 Typical IEEE 1588 Clock Addend Values
  159
- IEEE 1588 Clock/Events
  160
- IEEE 1588 Gpios
  160
- IEEE 1588 Interrupts
  160
Chapter 12 General Purpose Timer & Free-Running Clock

161
- General Purpose Timer
  161
- Free-Running Clock
  161
Chapter 13 GPIO/LED Controller

162
- Functional Overview
  162
- GPIO Operation
  162
- GPIO IEEE 1588 Timestamping
  163
- IEEE 1588 GPIO Inputs
  163
- IEEE 1588 GPIO Outputs
  163
- GPIO Interrupts
  163
- GPIO Interrupt Polarity
  163
- IEEE 1588 GPIO Interrupts
  164
- LED Operation
  164
- Table 13.1 LED Operation as a Function of LED_CFG[9:8]
  164
Chapter 14 Register Descriptions

166
Chapter 15 Operational Characteristics

440
Chapter 16 Package Outlines

454
Chapter 17 Revision History

458
- Table 17.1 Customer Revision History
  458

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SMSC LAN9312 Manuals

SMSC LAN9312 Datasheet (458 pages)

Table of Contents

Chapter 1 Preface

Chapter 2 Introduction

Chapter 3 Pin Description and Configuration

Chapter 4 Clocking, Resets, and Power Management

Chapter 5 System Interrupts

Chapter 6 Switch Fabric

Chapter 7 Ethernet Phys

Chapter 8 Host Bus Interface (HBI)

Chapter 9 Host MAC

Chapter 10 Serial Management

Chapter 11 IEEE 1588 Hardware Time Stamp Unit

Chapter 12 General Purpose Timer & Free-Running Clock

Chapter 13 GPIO/LED Controller

Chapter 14 Register Descriptions

Chapter 15 Operational Characteristics

Chapter 16 Package Outlines

Chapter 17 Revision History

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