SMSC LAN9312 Datasheet

High performance two port 10/100 managed ethernet switch with 32-bit non-pci cpu interface

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PRODUCT FEATURES

Highlights

High performance and full featured 2 port switch with

VLAN, QoS packet prioritization, Rate Limiting, IGMP

Snooping and management functions

Easily interfaces to most 32-bit embedded CPU's

Unique Virtual PHY feature simplifies software

development by mimicking the multiple switch ports

as a single port MAC/PHY

Integrated IEEE 1588 Hardware Time Stamp Unit

Target Applications

Cable, satellite, and IP set-top boxes

Digital televisions

Digital video recorders

VoIP/Video phone systems

Home gateways

Test/Measurement equipment

Industrial automation systems

Key Benefits

Ethernet Switch Fabric

— 32K buffer RAM

— 1K entry forwarding table

— Port based IEEE 802.1Q VLAN support (16 groups)

– Programmable IEEE 802.1Q tag insertion/removal

— IEEE 802.1d spanning tree protocol support

— QoS/CoS Packet prioritization

– 4 dynamic QoS queues per port

– Input priority determined by VLAN tag, DA lookup,

TOS, DIFFSERV or port default value

– Programmable class of service map based on input

priority

– Remapping of 802.1Q priority field on per port basis

– Programmable rate limiting at the ingress/egress

ports with random early discard, per port / priority

— IGMP v1/v2/v3 snooping for Multicast packet filtering

— IPV6 Multicast Listener Discovery snoop

— Programmable filter by MAC address

Switch Management

— Port mirroring/monitoring/sniffing: ingress and/or egress

traffic on any ports or port pairs

— Fully compliant statistics (MIB) gathering counters

— Control registers configurable on-the-fly

SMSC LAN9312

LAN9312

High Performance

Two Port 10/100 Managed

Ethernet Switch with 32-Bit

Non-PCI CPU Interface

Ports

— 2 internal 10/100 PHYs with HP Auto-MDIX support

— Fully compliant with IEEE 802.3 standards

— 10BASE-T and 100BASE-TX support

— Full and half duplex support

— Full duplex flow control

— Backpressure (forced collision) half duplex flow control

— Automatic flow control based on programmable levels

— Automatic 32-bit CRC generation and checking

— Automatic payload padding

— 2K Jumbo packet support

— Programmable interframe gap, flow control pause value

— Full transmit/receive statistics

— Auto-negotiation

— Automatic MDI/MDI-X

— Loop-back mode

High-performance host bus interface

— Provides in-band network communication path

— Access to management registers

— Simple, SRAM-like interface

— 32-bit data bus

— Big, little, and mixed endian support

— Large TX and RX FIFO's for high latency applications

— Programmable water marks and threshold levels

— Host interrupt support

IEEE 1588 Hardware Time Stamp Unit

— Global 64-bit tunable clock

— Master or slave mode per port

— Time stamp on TX or RX of Sync and Delay_req

packets per port, Timestamp on GPIO

— 64-bit timer comparator event generation (GPIO or IRQ)

Comprehensive Power Management Features

— Wake on LAN

— Wake on link status change (energy detect)

— Magic packet wakeup

— Wakeup indicator event signal

Other Features

— General Purpose Timer

— Serial EEPROM interface (I

master) for non-managed configuration

— Programmable GPIOs/LEDs

Single 3.3V power supply

Available in Commercial Temp. Range

DATASHEET

Datasheet

C master or Microwire

Revision 1.4 (08-19-08)

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Summary of Contents for SMSC LAN9312

Page 1: Product Features
PRODUCT FEATURES Highlights High performance and full featured 2 port switch with VLAN, QoS packet prioritization, Rate Limiting, IGMP Snooping and management functions Easily interfaces to most 32-bit embedded CPU’s Unique Virtual PHY feature simplifies software development by mimicking the multiple switch ports...
Page 2: Order Numbers
Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.
Page 3: Table Of Contents
Switch Fabric Interrupts ........
Page 4 Chapter 6 Switch Fabric ........
Page 5 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 7.2.1.6 100M Phase Lock Loop (PLL) ... 86 7.2.2 100BASE-TX Receive ............87 7.2.2.1...
Page 6 10.2.4 EEPROM Loader ............149 10.2.4.1 EEPROM Loader Operation ... 149 10.2.4.2 EEPROM Valid Flag ... 151 10.2.4.3 MAC Address... 151 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DATASHEET Datasheet SMSC LAN9312...
Page 7 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 10.2.4.3.1Host MAC Address Reload ...151 10.2.4.4 Soft-Straps ... 151 10.2.4.4.1PHY Registers Synchronization ...151 10.2.4.4.2Virtual PHY Registers Synchronization...152 10.2.4.4.3LED and Manual Flow Control Register Synchronization ...152 10.2.4.5 Register Data ...
Page 8 14.2.6 Switch Fabric ........
Page 9 Switch Fabric Control and Status Registers ........
Page 10 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) ... 401 14.5.3.33 Switch Engine Port 0 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_MII) ... 402 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) ... 403 14.5.3.35...
Page 11 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.6 Clock Circuit ..............453 Chapter 16 Package Outlines .
Page 12 Figure 2.2 System Block Diagram............25 Figure 3.1 LAN9312 128-VTQFP Pin Assignments (TOP VIEW) ......26 Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW).
Page 13 Figure 16.3 LAN9312 128-XVTQFP Package Definition........
Page 14 Table 4.1 Reset Sources and Affected LAN9312 Circuitry ....... . .
Page 15 Table 16.2 LAN9312 128-XVTQFP Dimensions ........
Page 16: Chapter 1 Preface
First In First Out buffer Finite State Machine General Purpose I/O Host Bus Interface. The physical bus connecting the LAN9312 to the host. Also referred to as the Host Bus. Host Bus Interface Controller. The hardware module that interfaces the LAN9312 to the HBI.
Page 17 “1” and leaves the signal unchanged for a “0” Not Applicable No Connect Organizationally Unique Identifier Refers to data output from the LAN9312 to the host Program I/O cycle. An SRAM-like read or write cycle on the HBI. Parallel In Serial Out Phase Locked Loop Precision Time Protocol Refers to a reserved bit field or address.
Page 18: Buffer Types
Note: Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on internal resistors to drive signals external to the LAN9312. When connected to a load that must be pulled high, an external resistor must be added. 50uA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-downs are always enabled.
Page 19: Register Nomenclature
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Register Nomenclature Table 1.2 describes the register bit attribute notation used throughout this document. REGISTER BIT TYPE NOTATION Read: A register or bit with this attribute can be read.
Page 20: Chapter 2 Introduction
Ethernet and Fast Ethernet applications. At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames.
Page 21: Block Diagram
IEEE 1588 System Clocks/ Time Stamp Interrupt Reset/PME Clock/Events Controller Free-Run Controller External 25MHz Crystal Figure 2.1 Internal LAN9312 Block Diagram Virtual PHY Registers Host MAC MDIO TX/RX FIFOs Host Bus Interface Register To 32-bit Access Host Bus EEPROM Loader...
Page 22: System Clocks/Reset/Pme Controller
A multi-module reset is initiated by assertion of the following: Digital Reset - DIGITAL_RST (bit 0) in the - Resets all LAN9312 sub-modules except the Ethernet PHYs (Port 1 PHY, Port 2 PHY, and Virtual PHY) Soft Reset - SRST (bit 0) in the...
Page 23: Switch Fabric
2.2.4 Ethernet PHYs The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port. These PHYs interface with their respective MAC via an internal MII interface.
Page 24: Host Mac
1588 Time Stamp module connected to each port via the MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock.
Page 25: Gpio/Led Controller
The LAN9312 utilizes the internal Host MAC to provide a network path for the host CPU. The LAN9312 may share the host bus with additional system memory and/or peripherals. For more information on the HBI, refer to...
Page 26: Chapter 3 Pin Description And Configuration
EXRES VDD33BIAS VDD18TX2 VDD33A2 RXP2 RXN2 VDD33A2 TXP2 TXN2 Figure 3.1 LAN9312 128-VTQFP Pin Assignments (TOP VIEW) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface SMSC LAN9312 128-VTQFP TOP VIEW DATASHEET Datasheet...
Page 27: 128-Xvtqfp Pin Diagram
VDD18TX1 EXRES VDD33BIAS VDD18TX2 VDD33A2 RXP2 RXN2 VDD33A2 TXP2 TXN2 Figure 3.2 LAN9312 128-XVTQFP Pin Assignments (TOP VIEW) SMSC LAN9312 SMSC LAN9312 128-XVTQFP TOP VIEW NOTE: EXPOSED PAD ON BOTTOM OF PACKAGE MUST BE CONNECTED TO GROUND DATASHEET VDD33IO END_SEL...
Page 28: Pin Descriptions
Pin Descriptions This section contains the descriptions of the LAN9312 pins. The pin descriptions have been broken into functional groups as follows: LAN Port 1 Pins LAN Port 2 Pins LAN Port 1 & 2 Power and Common Pins Host Bus Interface Pins...
Page 29: Table 3.2 Lan Port 2 Pins
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Note 3.1 The pin names for the twisted pair pins apply to a normal connection. If HP Auto-MDIX is enabled and a reverse connection is detected or manually selected, the RX and TX pins will be swapped internally.
Page 30: Table 3.4 Host Bus Interface Pins
49-53, Read Strobe Write Strobe Chip Select Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface BUFFER TYPE +3.3V Port 2 Analog Power Supply Refer to the LAN9312 application note for additional connection information.
Page 31: Table 3.5 Eeprom Pins
BUFFER TYPE Data FIFO Direct Access Select: When driven high, all accesses to the LAN9312 are directed to the RX and TX Data FIFO’s. All reads are from the RX Data FIFO, and all writes are to the TX Data FIFO.
Page 32: Table 3.6 Dedicated Configuration Strap Pins
LED_EN Strap PHY Address PHY_ADDR_SEL Strap Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 3.5 EEPROM Pins (continued) BUFFER TYPE EECS EEPROM Microwire Chip Select: In Microwire EEPROM mode (EEPROM_TYPE = 0), this pin is the Microwire EEPROM chip select output.
Page 33: Table 3.7 Miscellaneous Pins
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 3.6 Dedicated Configuration Strap Pins (continued) NAME SYMBOL Port 1 Auto- AUTO_MDIX_1 MDIX Enable Strap Port 2 Auto- AUTO_MDIX_2 MDIX Enable Strap Note: For more information on configuration straps, refer to page 40.
Page 34: Table 3.8 Pll Pins
VDD18CORE +1.8V Power Supply 3,14,40,65, Output 74,88,104 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface BUFFER TYPE TEST1 Test 1: This pin must be tied to VDD33IO for proper operation. TEST2 Test 2: This pin must be tied to VDD33IO for proper operation.
Page 35: Table 3.10 No-Connect Pins
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 3.9 Core and I/O Power and Ground Pins (continued) NAME SYMBOL 18,48,80, Common 97,112,113, Ground Note 3.8 Note 3.8 Plus external pad for 128-XVTQFP package only...
Page 36: Chapter 4 Clocking, Resets, And Power Management
453. Resets The LAN9312 provides multiple hardware and software reset sources, which allow varying levels of the LAN9312 to be reset. All resets can be categorized into three reset types as described in the following sections: Chip-Level Resets —Power-On Reset (POR) —nRST Pin Reset...
Page 37: Chip-Level Resets
4.2.1.1 Power-On Reset (POR) A power-on reset occurs whenever power is initially applied to the LAN9312, or if the power is removed and reapplied to the LAN9312. This event resets all circuitry within the device. Configuration straps are latched, and the EEPROM Loader is run as a result of this reset.
Page 38: Nrst Pin Reset
Writes to any address are invalid until the READY bit is set. Note: The digital reset and soft reset do not reset register bits designated as NASR. Note: The LAN9312 must be read at least once after a multi-module reset to ensure that write operations function properly.
Page 39: Soft Reset (Srst)
Upon completion of the Port 2 PHY reset, the PHY2_RST and Reset bits are automatically cleared. No other modules of the LAN9312 are affected by this reset. In addition to the methods above, the Port 2 PHY is automatically reset after returning from a PHY power-down mode.
Page 40: Virtual Phy Reset
4.2.4 Configuration Straps Configuration straps allow various features of the LAN9312 to be automatically configured to user defined values. Configuration straps can be organized into two main categories: hard-straps and soft- straps. Both hard-straps and soft-straps are latched upon Power-On Reset (POR) or pin reset (nRST).
Page 41: Table 4.2 Soft-Strap Configuration Strap Definitions
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions STRAP NAME DESCRIPTION LED_en_strap[7:0] LED Enable Straps: Configures the default value for the LED_EN bits in the (LED_CFG). A high value configures the associated LED/GPIO pin as a LED.
Page 42 When configured high, full- duplex Pause packet detection and generation are enabled. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Speed Select LSB (PHY_SPEED_SEL_LSB) Section Port x PHY Basic...
Page 43 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) STRAP NAME DESCRIPTION manual_FC_strap_1 Port 1 Manual Flow Control Enable Strap: Configures the default value of the Select (MANUAL_FC_1)
Page 44 When configured high, full- duplex Pause packet detection and generation are enabled. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Speed Select LSB (PHY_SPEED_SEL_LSB) Section Port x PHY Basic...
Page 45: Hard-Straps
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 4.2 Soft-Strap Configuration Strap Definitions (continued) STRAP NAME DESCRIPTION manual_FC_strap_2 Port 2 Manual Flow Control Enable Strap: Configures the default value of the Select (MANUAL_FC_2)
Page 46: Power Management
PHYs and Virtual PHY as detailed in Power Management The LAN9312 Port 1 and Port 2 PHYs and the Host MAC support several power management and wakeup features. The LAN9312 can be programmed to issue an external wake signal (PME) via several methods, including wake on LAN, wake on link status change (energy detect), and magic packet wakeup.
Page 47: Port 1 & 2 Phy Power Management
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet WUFR (bit 6) of HMAC_WUCSR register WUEN (bit 2) of HMAC_WUCSR register MPR (bit 5) of HMAC_WUCSR register MPEN (bit 1) of HMAC_WUCSR register INT7 (bit 7) of...
Page 48: Host Mac Power Management
Refer to Section 9.5, "Wake-up Frame Detection," on page 116 Detection," on page 118 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface (PMT_CTRL). Power Management Control Register (PMT_CTRL) (PMT_CTRL). for additional details on these features.
Page 49: Chapter 5 System Interrupts
Chapter 5 System Interrupts Functional Overview This chapter describes the system interrupt structure of the LAN9312. The LAN9312 provides a multi- tier programmable interrupt structure which is controlled by the System Interrupt Controller. The programmable system interrupts are generated internally by the various LAN9312 sub-modules and can be configured to generate a single external host interrupt via the IRQ interrupt output pin.
Page 50: Figure 5.1 Functional Interrupt Register Hierarchy
INT_STS register Bit 12 (GPIO) of INT_STS register Figure 5.1 Functional Interrupt Register Hierarchy Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1588 Time Stamp Interrupt Register 1588_INT_STS_EN Switch Fabric Interrupt Registers SW_IMR...
Page 51: 1588 Time Stamp Interrupts
The following sections detail each category of interrupts and their related registers. Refer to Chapter 14, "Register Descriptions," on page 166 5.2.1 1588 Time Stamp Interrupts Multiple 1588 Time Stamp interrupt sources are provided by the LAN9312. The top-level 1588_EVNT (bit 29) of the Interrupt Status Register (INT_STS) occurred in the...
Page 52: Ethernet Phy Interrupts
5.2.4 GPIO Interrupts Each GPIO[11:0] of the LAN9312 is provided with its own interrupt. The top-level GPIO (bit 12) of the Interrupt Status Register (INT_STS) General Purpose I/O Interrupt Status and Enable Register Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) and status of each GPIO[11:0] interrupt.
Page 53: Power Management Interrupts
Host MAC operation. 5.2.6 Power Management Interrupts Multiple Power Management Event interrupt sources are provided by the LAN9312. The top-level PME_INT (bit 17) of the Management interrupt event occurred in the Power Management Control Register (PMT_CTRL) Power Management conditions.
Page 54: Software Interrupt
A device ready interrupt is provided in the top-level Enable Register (INT_EN). The READY interrupt (bit 30) of the indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. Writing a 1 to this bit in the Interrupt Status Register (INT_STS)
Page 55: Chapter 6 Switch Fabric
Chapter 6 Switch Fabric Functional Overview At the core of the LAN9312 is the high performance, high efficiency 3 port Ethernet switch fabric. The switch fabric contains a 3 port VLAN layer 2 switch engine that supports untagged, VLAN tagged, and priority tagged frames.
Page 56: Switch Fabric Csr Writes
Datasheet 6.2.1 Switch Fabric CSR Writes To perform a write to an individual switch fabric register, the desired data must first be written into the Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA). The write cycle is initiated by p e r f o r m i n g a s i n g l e w r i t e t o t h e...
Page 57: Switch Fabric Csr Reads
Figure 6.1 Switch Fabric CSR Write Access Flow Diagram 6.2.2 Switch Fabric CSR Reads To perform a read of an individual switch fabric register, the read cycle must be initiated by performing a single write to the Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) CSR_BUSY (bit 31) set, the CSR_ADDRESS field (bits 15:0) set to the desired register address, the R_nW (bit 30) set, and the AUTO_INC and AUTO_DEC fields cleared.
Page 58: Flow Control Enable Logic
6.2.3 Flow Control Enable Logic Each switch fabric port (0,1,2) is provided with two flow control enable inputs per port, one for transmission and one for reception. Flow control on transmission allows the transmitter to generate back pressure in half-duplex mode, and pause packets in full-duplex. Flow control in reception enables the reception of pause packets to pause transmissions.
Page 59: Table 6.1 Switch Fabric Flow Control Enable Logic
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet register. When Auto-negotiation is enabled and the MANUAL_FC_x bit is cleared, the switch port flow control enables during full-duplex are determined by Auto-negotiation. Note: The flow control values in the...
Page 60: 10/100 Ethernet Macs
Case 11 - Asymmetric pause from partner (towards switch port) 10/100 Ethernet MACs The switch fabric contains three 10/100 MAC blocks, one for each switch port (0,1,2). The 10/100 MAC provides the basic 10/100 Ethernet functionality, including transmission deferral and collision back- off/retry, receive/transmit FCS checking and generation, receive/transmit pause flow control, and transmit back pressure.
Page 61: Receive Counters
The size of the RX FIFO is 256 bytes. If a bad packet with less than 64 bytes is received, it will be flushed from the FIFO automatically and the FIFO space recovered. Packets equal to or larger than 64 bytes with an error will be marked and reported to the switch engine. The switch engine will subsequently drop the packet.
Page 62: Transmit Mac
The auto-padding and FCS generation is controlled via the TX Pad Enable bit of the Transmit Configuration Register The transmit FIFO acts as a temporary buffer between the transmit MAC and the switch engine. The FIFO logic manages the re-transmission for normal collision conditions or discards the frames for late or excessive collisions.
Page 63: Switch Engine (Swe)
Total collision count Switch Engine (SWE) The switch engine (SWE) is a VLAN layer 2 (link layer) switching engine supporting 3 ports. The SWE supports the following types of frame formats: untagged frames, VLAN tagged frames, and priority tagged frames. The SWE supports both the 802.3 and Ethernet II frame formats.
Page 64: Learning/Aging/Migration
Engine ALR Write Data 0 Register Register (SWE_ALR_WR_DAT_1). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface (SWE_PORT_INGRSS_CFG). for additional details. S w i t c h E n g i n e...
Page 65 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet The following procedure should be followed in order to add, delete, and modify the ALR entries: 1. Write the Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) ALR Write Data 1 Register (SWE_ALR_WR_DAT_1) bits.
Page 66: Forwarding Rules
If there is insufficient buffer space, the packet is discarded. When the switch is enabled for VLAN support, these following rules also apply: If the packet is untagged or priority tagged and the Admit Only VLAN bit for the ingress port is set, the packet is filtered.
Page 67: Transmit Priority Queue Selection
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 6.4.3 Transmit Priority Queue Selection The transmit priority queue may be selected from five options. As shown in be based on: the static value for the destination address in the ALR table...
Page 68: Figure 6.5 Switch Engine Transmit Queue Calculation
Queue = ALR Priority Figure 6.5 Switch Engine Transmit Queue Calculation Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for definitions of the configuration bits. Get Queue Packet from Host DA Highest...
Page 69: Port Default Priority
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 6.4.3.1 Port Default Priority As detailed in Figure 6.5, the default priority is based on the ingress ports priority bits in its port VID value. The PVID table is read and written by using the...
Page 70: Vlan Support
6.4.4 VLAN Support The switch engine supports 16 active VLANs out of a possible 4096. The VLAN table contains the 16 active VLAN entries, each consisting of the VID, the port membership, and un-tagging instructions. Member Un-tag Member Port 2...
Page 71: Ingress Flow Metering And Coloring
6.4.6 Ingress Flow Metering and Coloring The LAN9312 supports hardware ingress rate limiting by metering packet streams and marking packets as either Green, Yellow, or Red according to three traffic parameters: Committed Information Rate (CIR), Committed Burst Size (CBS), and Excess Burst Size (EBS). A packet is marked Green if it does not exceed the CBS, Yellow if it exceeds to CBS but not the EBS, or Red otherwise.
Page 72: Ingress Flow Calculation
The VLAN tag priority field (but not through the per port Priority Regeneration table) The port default Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 6.3 Typical Ingress Rate Settings 80 nS...
Page 73: Figure 6.7 Switch Engine Ingress Flow Priority Selection
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Packet is from Host Packet is Tagged VL Higher Priority Use Precedence IPv4(TOS) IPv6(TC) IPv4 Precedence Source Port VLAN Priority Figure 6.7 Switch Engine Ingress Flow Priority Selection...
Page 74: Broadcast Storm Control
6.4.7 Broadcast Storm Control In addition to ingress rate limiting, the LAN9312 supports hardware broadcast storm control on a per port basis. This feature is enabled via the (SWE_BCST_THROT). The allowed rate per port is specified as the number of bytes multiplied by 64 allowed to be received every 1.72 mS interval.
Page 75: Port Mirroring
VLAN. 6.4.9 Port Mirroring The LAN9312 supports port mirroring where packets received or transmitted on a port or ports can also be copied onto another “sniffer” port. Port mirroring is configured using the Multiple mirrored ports can be defined, but only one sniffer port can be defined.
Page 76: Packets To The Host Cpu
VID field. Note: The maximum size tagged packet that can normally be sent into a switch port (from the Host MAC) is 1522 bytes. Since the special tag consumes four bytes of the packet length, the outgoing packet is limited to 1518 bytes, even if it contains a regular VLAN tag as part of the packet data.
Page 77: Buffer Manager (Bm)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Buffer Manager (BM) The buffer manager (BM) provides control of the free buffer space, the multiple priority transmit queues, transmission scheduling, and packet dropping. VLAN tag insertion and removal is also performed by the buffer manager.
Page 78: Transmit Priority Queue Servicing
The egress limiting is enabled per priority queue. After a packet is selected to be sent, its length is recorded. The switch then waits a programmable amount of time, scaled by the packet length, before servicing that queue once again. The amount of time per byte is programmed into the Buffer Manager Egress Rate registers (refer to definitions).
Page 79: Adding, Removing, And Changing Vlan Tags
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 6.5.6 Adding, Removing, and Changing VLAN Tags Based on the port configuration and the received packet formation, a VLAN tag can be added to, removed from, or modified in a packet. There are four received packet type cases: non-tagged, priority- tagged, normal-tagged, and CPU special-tagged.
Page 80: Figure 6.9 Hybrid Port Tagging And Un-Tagging
Buffer Manager Port 1 Default VLAN ID and Priority Register (BM_VLAN_1) Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Figure 6.9.
Page 81: Counters
Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) Buffer Manager Port 2 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_2) Switch Fabric Interrupts The switch fabric is capable of generating multiple maskable interrupts from the buffer manager, switch engine, and MACs. These interrupts are detailed in page SMSC LAN9312 Section 5.2.2, "Switch Fabric Interrupts,"...
Page 82: Chapter 7 Ethernet Phys
Chapter 7 Ethernet PHYs Functional Overview The LAN9312 contains three PHYs: Port 1 PHY, Port 2 PHY and a Virtual PHY. The Port 1 & 2 PHYs are identical in functionality and each connect their corresponding Ethernet signal pins to the switch fabric MAC of their respective port.
Page 83: Port 1 & 2 Phys
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Port 1 & 2 PHYs Functionally, each PHY can be divided into the following sections: 100BASE-TX Transmit 10BASE-T Transmit PHY Auto-negotiation HP Auto-MDIX MII MAC Interface PHY Management Control Note 7.1...
Page 84: 100Base-Tx Transmit
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
Page 85: Table 7.2 4B/5B Code Table
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet CODE GROUP 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 IDLE 11000 First nibble of SSD, translated to “0101”...
Page 86: Scrambler And Piso
The 100M PLL locks onto the reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the 100BASE-TX Transmitter. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 7.2 4B/5B Code Table (continued) RECEIVER...
Page 87: 100Base-Tx Receive
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 7.2.2 100BASE-TX Receive The 100BASE-TX receive data path is shown in to the PHY. Each major block is explained in the following sections. Internal MII Receive Clock...
Page 88: Nrzi And Mlt-3 Decoding
(bad SSD error), RXER is asserted and the value 1110b is driven onto the internal receive data bus (RXD) to the switch fabric MAC. Note that the internal MII’s data valid signal (RXDV) is not yet asserted when the bad SSD occurs.
Page 89: 10Base-T Transmit
For a transmission, the switch fabric MAC drives the transmit data to the PHYs MII MAC Interface. The MII MAC Interface is described in detail in Note: The PHY is connected to the switch fabric MAC via standard MII signals. Refer to the IEEE 802.3 specification for additional details.
Page 90: Mii Mac Interface
IEEE 802.3 specification. The LAN9312 does not support “Next Page” capability. Many of the default advertised capabilities of the PHY are determined via configuration straps as shown in Negotiation Advertisement Register (PHY_AN_ADV_x),"...
Page 91 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 10M PLL (analog) 10M TX Driver (analog) Auto-negotiation is started by the occurrence of any of the following events: Power-On Reset (POR) Hardware reset (nRST) PHY Software reset (via...
Page 92: Phy Pause Flow Control
7.2.5.2 Parallel Detection If the LAN9312 is connected to a device lacking the ability to auto-negotiate (i.e. no FLPs are detected), it is able to determine the speed of the link based on either 100M MLT-3 symbols or 10M Normal Link Pulses. In this case the link is presumed to be half-duplex per the IEEE 802.3 standard.
Page 93: Half Vs. Full-Duplex
MII MAC Interface The MII MAC Interface is responsible for the transmission and reception of the Ethernet data to and from the switch fabric MAC. The PHY is connected internally to the switch fabric MAC via standard MII signals per IEEE 802.3.
Page 94: Phy Management Control
System Interrupt Controller and is reflected via the the Port 1 PHY, and bit 27 (PHY_INT2) for the Port 2 PHY. For more information on the LAN9312 interrupts, refer to Chapter 5, "System Interrupts,"...
Page 95: Phy General Power-Down
The energy detect power down feature is part of the broader power management features of the LAN9312 and can be used to trigger the power management event output pin (PME). This is accomplished by enabling the energy detect power-down feature of the PHY as described above, and...
Page 96: Phy Software Reset Via Phy_Basic_Ctrl_X
802.3 (clause 22) so that an unmodified driver can be supported as if the Host MAC was attached to a single port PHY. This functionality is designed to allow easy and quick integration of the LAN9312 into designs with minimal driver modifications. The Virtual PHY provides a full bank of registers which comply with the IEEE 802.3 specification.
Page 97: Parallel Detection
Note: For the Virtual PHY, the auto-negotiation register bits (and management of such) are used by the Host MAC. So the perception of local and link partner is reversed. The local device is the Host MAC, while the link partner is the switch fabric. This is consistent with the intention of the Virtual PHY.
Page 98: Virtual Phy Pause Flow Control
In addition to the chip-level hardware reset (nRST) and Power-On Reset (POR), the Virtual PHY supports three block specific resets. These are is discussed in the following sections. For detailed information on all LAN9312 resets, refer to 7.3.2.1 Virtual PHY Software Reset via RESET_CTL The Virtual PHY can be reset via the (VPHY_RST).
Page 99: Chapter 8 Host Bus Interface (Hbi)
System Control and Status Registers (CSRs). These registers are accessible to the host via the Host Bus Interface and allow direct (and indirect) access to all the LAN9312 functions. For a full list of all System CSR’s and their descriptions, refer to Registers".
Page 100: Figure 8.1 Little Endian Byte Ordering
Data path operations for the supported endian configurations are illustrated in Figure 8.1, "Little Endian Byte Ordering" and Figure 8.2, "Big Endian Byte Ordering". Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 32-BIT LITTLE ENDIAN (END_SEL = 0)
Page 101: Host Interface Timing
These restrictions concern reading the host control registers after any write cycle to the LAN9312. In some cases there is a delay between writing to the LAN9312, and the subsequent side effect (change in the control register value). For example, when writing to the TX Data FIFO, it takes...
Page 102: Table 8.1 Read After Write Timing Rules
1588_CLOCK_HI_RX_CAPTURE_1 1588_CLOCK_LO_RX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_1 1588_SRC_UUID_LO_RX_CAPTURE_1 1588_CLOCK_HI_TX_CAPTURE_1 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 8.1 Read After Write Timing Rules MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) DATASHEET...
Page 103 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 8.1 Read After Write Timing Rules (continued) REGISTER NAME 1588_CLOCK_LO_TX_CAPTURE_1 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_1 1588_SRC_UUID_LO_TX_CAPTURE_1 1588_CLOCK_HI_RX_CAPTURE_2 1588_CLOCK_LO_RX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_2 1588_SRC_UUID_LO_RX_CAPTURE_2 1588_CLOCK_HI_TX_CAPTURE_2 1588_CLOCK_LO_TX_CAPTURE_2 1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_2 1588_SRC_UUID_LO_TX_CAPTURE_2 1588_CLOCK_HI_RX_CAPTURE_MII 1588_CLOCK_LO_RX_CAPTURE_MII 1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_MII 1588_SRC_UUID_LO_RX_CAPTURE_MII 1588_CLOCK_HI_TX_CAPTURE_MII...
Page 104 GPIO_CFG GPIO_DATA_DIR GPIO_INT_STS_EN SWITCH_MAC_ADDRH SWITCH_MAC_ADDRL RESET_CTL SWITCH_CSR_DIRECT_DATA Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface MINIMUM WAIT TIME FOR READ FOLLOWING ANY WRITE CYCLE (IN NS) DATASHEET Datasheet NUMBER OF BYTE_TEST READS...
Page 105: Special Restrictions On Back-To-Back Read Cycles
There are also restrictions on specific back-to-back host read operations. These restrictions concern reading specific registers after reading a resource that has side effects. In many cases there is a delay between reading the LAN9312, and the subsequent indication of the expected change in the control and status register values.
Page 106: Pio Reads
END_SEL A[x:2] nCS, nRD D[31:0] (OUTPUT) Figure 8.3 Functional Timing for PIO Read Operation Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for information on these restrictions. VALID VALID VALID DATASHEET Datasheet 446.
Page 107: Pio Burst Reads
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 8.4.5 PIO Burst Reads In this mode, performance is improved by allowing up to 8 DWORD read cycles back-to-back. PIO burst reads can be performed using Chip Select (nCS) or Read Enable (nRD). A PIO Burst Read begins when both nCS and nRD are asserted.
Page 108: Rx Data Fifo Direct Pio Reads
RX Data FIFO Direct PIO Reads In this mode only A[2] is decoded, and any read of the LAN9312 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 109: Rx Data Fifo Direct Pio Burst Reads
RX Data FIFO Direct PIO Burst Reads In this mode only A[2] is decoded, and any burst read of the LAN9312 will read the RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 110: Pio Writes
8.4.8 PIO Writes PIO writes are used for all LAN9312 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable (nWR). A PIO write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS and nWR are de-asserted. Either or both of these control signals must...
Page 111: Tx Data Fifo Direct Pio Writes
TX Data FIFO Direct PIO Writes In this mode only A[2] is decoded, and any write to the LAN9312 will write the TX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the FIFO_SEL signal to a high-order address line.
Page 112: Chapter 9 Host Mac
Host Bus Interface (HBI) and the Ethernet PHYs and Switch Fabric. On the front end, the Host MAC interfaces to the HBI via 2 sets of FIFO’s (TX Data FIFO, TX Status FIFO, RX Data FIFO, RX Status FIFO). An additional bus is used to access the Host MAC CSR’s via the...
Page 113: Flow Control
System CSR space and the Host MAC CSR space. Note: The Host MAC controls the flow between the switch fabric and the Host MAC, not the network flow control. The switch fabric handles the network flow control independently.
Page 114: Address Filtering
Note: This filtering function is performed after any switch fabric filtering functions. The user must ensure the switch filtering is setup properly to allow packets to be passed to the Host MAC for further filtering.
Page 115: Perfect Filtering
9.4.2 Hash Only Filtering This type of filtering checks for incoming receive packets (from switch Port 0) with either multicast or physical destination addresses, and executes an imperfect address filtering against the hash table. The hash table is formed by merging the values in the...
Page 116: Inverse Filtering
Note: The switch fabric must be configured to pass wake-up packets to the Host MAC for this function to operate properly. Note: When wake-up frame detection is enabled via the WUEN bit of the...
Page 117: Table 9.2 Wake-Up Frame Filter Register Structure
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 9.2 Wake-Up Frame Filter Register Structure Reserved Filter 3 Reserved Command Filter 3 Offset Filter 2 Offset Filter 1 CRC-16 Filter 3 CRC-16 The Filter i Byte Mask defines which incoming frame bytes Filter i will examine to determine whether or not this is a wake-up frame.
Page 118: Magic Packet Detection
Host MAC examines received data for a Magic Packet. The LAN9312 can be programmed to notify the host of the “Magic Packet” detection with the assertion of the host interrupt (IRQ) or power management event signal (PME). Upon detection, the Magic Packet Received bit (MPR) in the HMAC_WUCSR register is set.
Page 119: Host Mac Address
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 …CRC Note: The switch fabric must be configured to pass magic packets to the Host MAC for this function to operate properly.
Page 120: Fifos
For more information on the EEPROM and EEPROM Loader, refer to Master EEPROM Controller," on page FIFOs The LAN9312 contains four host-accessible FIFOs (TX Status, RX Status, TX Data, and RX Data) and two internal inaccessible Host MAC TX/RX MIL FIFO’s (TX MIL FIFO, RX MIL FIFO). 9.7.1...
Page 121: Fifo Memory Allocation Configuration
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet reception, the data must be moved into the RX FIFOs before the host can access the data. For TX operations, the MIL operates in store-and-forward mode and will queue an entire frame before beginning transmission.
Page 122: Tx Data Path Operation
Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’). The TX command instructs the LAN9312 on the handling of the associated buffer. Packet boundaries are delineated using control bits within the TX command.
Page 123: Figure 9.3 Simplified Host Tx Flow Diagram
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet The LAN9312 can be programmed to strip padding from the end of a transmit packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9312 is operating in a system that always performs multi-word bursts.
Page 124: Tx Buffer Format
Figure 9.4 shows the TX Buffer as it is written into the LAN9312. It should be noted that not all of the data shown in this diagram is actually stored in the TX Data FIFO. This must be taken into account when calculating the actual TX Data FIFO usage.
Page 125: Tx Command 'A
This value, along with the Buffer End Alignment field, is read and checked by the LAN9312 and used to determine how many extra DWORDs were added to the end of the Buffer. A running count is also maintained in the LAN9312 of the cumulative buffer sizes for a given packet.
Page 126: Tx Command 'B
4 bytes in length The final buffer of any transmit packet can be any length Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 9.11 TX Command 'B' Format DESCRIPTION Table 9.12, "TX DATA Start Table 9.12 TX DATA Start Offset...
Page 127: Calculating Worst-Case Tx Mil Fifo Usage
TX Status FIFO overruns. In this mode the host is responsible for re-synchronizing TX status in the case of an overrun. Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events described in the TX Status word may still occur.
Page 128: Calculating Actual Tx Data Fifo Usage
0-Byte “Data Start Offset” 15-Bytes of payload data 16-Byte “Buffer End Alignment” Buffer 2: 10-Byte “Data Start Offset” 17-Bytes of payload data Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet SMSC LAN9312...
Page 129: Figure 9.5 Tx Example 1
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 16-Byte “Buffer End Alignment” Figure 9.5 illustrates the TX command structure for this example, and also shows how data is passed to the TX Data FIFO.
Page 130: Tx Example 2
TX Command 'B' Packet Length = 183 183-Byte Payload Data Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface TX Command 'A' TX Command 'B' 3B End Padding Figure 9.6 TX Example 2...
Page 131: Transmitter Errors
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 9.8.7 Transmitter Errors If the Transmitter Error (TXE) flag is asserted for any reason, the transmitter will continue operation. TX Error (TXE) will be asserted under the following conditions: If the actual packet length count does not match the Packet Length field as defined in the TX command.
Page 132: Rx Data Path Operation
RX packet read. The LAN9312 can be programmed to add padding at the end of a receive packet in the event that the end of the packet does not align with the host burst boundary. This feature is necessary when the LAN9312 is operating in a system that always performs multi-DWORD bursts.
Page 133: Figure 9.7 Host Receive Routine Using Interrupts
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Last Packet Figure 9.7 Host Receive Routine Using Interrupts Last Packet Figure 9.8 Host Receive Routine Using Polling SMSC LAN9312 init Idle RX Interrupt Read RX...
Page 134: Receive Data Fifo Fast Forward
The RX data path implements an automatic data discard function. Using the RX Data FIFO Fast Forward bit (RX_FFWD) in the instruct the LAN9312 to skip the packet at the head of the RX Data FIFO. The RX Data FIFO pointers are automatically incremented to the beginning of the next RX packet.
Page 135: Rx Status Format
RX Status FIFO, to ascertain the data size and any error conditions. 9.9.3 RX Status Format Note: Though the Host MAC is communicating locally with the switch fabric MAC, the events described in the RX Status word may still occur. BITS Reserved.
Page 136: Stopping And Starting The Receiver
An overrun of the RX Status FIFO It is the duty of the host to identify and resolve any error conditions. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION Host MAC Control Register...
Page 137: Chapter 10 Serial Management
The I The EEPROM Loader provides the automatic loading of configuration settings from the EEPROM into the LAN9312 at reset. The EEPROM Loader module interfaces to the EEPROM Controller, Ethernet PHYs, and the system CSRs. 10.2...
Page 138: Eeprom Controller Operation
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the EWEN command must first be issued. If an operation is attempted and the EEPROM device does not respond within 30mS, the LAN9312 will time-out, and the EPC_TIMEOUT bit of the Revision 1.4 (08-19-08)
Page 139: I2C Eeprom
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Figure 10.1 illustrates the process required to perform an EEPROM read or write operation. EEPROM Write E2P_DATA Register E2P_CMD Register E2P_CMD EPC_BUSY = 0 Register Figure 10.1 EEPROM Access Flow Diagram 10.2.2...
Page 140: I2C Protocol Overview
This informs the slave to not drive the next byte of data so that the master may generate a stop or repeated start condition. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface C operation are shown in Table Table 10.2 I...
Page 141: I2C Eeprom Device Addressing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Figure 10.2 displays the various bus states of a typical I data change EE_SDA EE_SCL Start Condition 10.2.2.2 C EEPROM Device Addressing The I C EEPROM is addressed for a read or write operation by first sending a control byte followed by the address byte or bytes.
Page 142: I2C Eeprom Byte Read
R/~W Select Bits Figure 10.5 I Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface EEPROM Command Register (E2P_CMD) C EEPROM byte read for single and double byte addressing. Control Byte S 1 0 1 0...
Page 143: I2C Eeprom Byte Writes
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Sequential reads are used by the EEPROM Loader. Refer to additional information. For a register level description of a read operation, refer to Operation," on page 138.
Page 144: Microwire Eeprom
INST OPCODE ERASE ERAL Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface EEPROM Command Register (E2P_CMD). Within each size range, the EEPROM SIZE 128 x 8 256 x 8 and 512 x 8...
Page 145: Erase (Erase Location)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 10.5 Microwire Command Set for 9 Address Bits (continued) START INST OPCODE EWDS EWEN READ WRITE WRAL Table 10.6 Microwire Command Set for 11 Address Bits...
Page 146: Eral (Erase All)
EWEN command must be issued. EECS EECLK EEDO EEDI Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface EEPROM Command Register (E2P_CMD) Figure 10.8 EEPROM ERAL Cycle Figure 10.9 EEPROM EWDS Cycle DATASHEET Datasheet...
Page 147: Ewen (Erase/Write Enable)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 10.2.3.5 EWEN (Erase/Write Enable) This command enables the EEPROM for erase and write operations. The EEPROM will allow erase and write operations until the EWDS command is sent, or until power is cycled.
Page 148: Write (Write Location)
EECLK EEDO EEDI Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface to be written to the EEPROM location pointed to by the EEPROM Command Register (E2P_CMD). The EPC_TIMEOUT bit of the is set if the EEPROM does not respond within 30mS.
Page 149: Eeprom Loader
(E2P_CMD), the EPC_BUSY bit in the While the EEPROM Loader is active, the READY bit of the (HW_CFG) Power Management Control Register (PMT_CTRL) LAN9312 should be attempted. The operational flow of the EEPROM Loader can be seen in Figure 10.14. SMSC LAN9312...
Page 150: Figure 10.14Eeprom Loader Flow Diagram
Byte 12 = A5h Perform register data load loop Figure 10.14 EEPROM Loader Flow Diagram Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Load PHY registers with current straps Load PHY registers with current straps...
Page 151: Eeprom Valid Flag
(HW_CFG)), the EEPROM Loader will read byte 0. If the byte Table 10.8. If the flag byte is not A5h, these next 4 bytes are skipped Section for more information on the LAN9312 configuration straps. Table 10.8 EEPROM Configuration Bits manual_ manual_mdix...
Page 152: 4.2Virtual Phy Registers Synchronization
Optionally following the configuration strap values, the EEPROM data may be formatted to allow access to the LAN9312 parallel, directly writable registers. Access to indirectly accessible registers (e.g. Switch Engine registers, etc.) is achievable with an appropriate sequence of writes (at the cost of EEPROM space).
Page 153: Eeprom Loader Finished Wait-State
In order to allow the EEPROM Loader to change the Port 1/2 PHYs and Virtual PHY strap inputs and maintain consistency with the PHY and Virtual PHY registers, the following sequence is used: 1. After power-up or upon a hardware reset (nRST), the straps are sampled into the LAN9312 as specified in Section 15.5.2, "Reset and Configuration Strap Timing,"...
Page 154: Chapter 11 Ieee 1588 Hardware Time Stamp Unit
MII bus. Any port may function as a master or a slave clock per the IEEE 1588 specification, and the LAN9312 as a whole may function as a boundary clock. A 64-bit tunable clock is provided that is used as the time source for all IEEE 1588 time stamp related functions.
Page 155: Block Diagram
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 11.1.2 Block Diagram The LAN9312 IEEE 1588 implementation is illustrated in major function blocks: IEEE 1588 Time Stamp These three identical blocks provide time stamping functions on all switch fabric ports.
Page 156: Ieee 1588 Time Stamp
PHY. This is consistent with the point-of-view of where the partner clock resides (LAN9312 receives packets from the partner via the PHY, etc.). For the time stamp module connected to the Host MAC (Port 0), the definition of transmit and receive is reversed. Receive is defined as data from the switch fabric, while transmit is defined as data to the switch fabric.
Page 157: Capture Locking
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Clock synchronization and hardware processing between the network data and the time stamp capture hardware causes the time stamp point to be slightly delayed. The host software can account for this delay, as it is fairly deterministic.
Page 158: Ptp Message Detection
11.2.2 PTP Message Detection In order to provide the most flexibility, loose packet type matching is used by the LAN9312. This assumes that for all packets received with a valid FCS, only the MAC destination address is required to qualify them as a PTP message. For Ethernet, four multicast addresses are specified in the PTP protocol: 224.0.1.129 through 224.0.1.132.
Page 159: Ieee 1588 Clock
Datasheet 11.3 IEEE 1588 Clock The 64-bit IEEE 1588 clock is the time source for all IEEE 1588 related functions of the LAN9312. It is readable and writable by the host via the 1588 Clock Low-DWORD Register In order to accurately read this clock, a special procedure must be followed. Since two DWORD reads are required to fully read the 64-bit clock, the possibility exists that as the lower 32-bits roll over, a wrong intermediate value could be read.
Page 160: Ieee 1588 Clock/Events
Refer to Chapter 5, "System Interrupts," on page 49 interrupts. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1588 Clock Target High-DWORD Register a n d 1 5 8 8 C l o c k...
Page 161: Chapter 12 General Purpose Timer & Free-Running Clock
This chapter details the LAN9312 General Purpose Timer (GPT) and the Free-Running Clock. 12.1 General Purpose Timer The LAN9312 provides a 16-bit programmable General Purpose Timer that can be used to generate periodic system interrupts. The resolution of this timer is 100uS. The GPT loads the...
Page 162: Chapter 13 Gpio/Led Controller
Note: For GPIO[9:8], the pin direction is a function of both the GPDIR[9:8] bits of the Purpose I/O Data & Direction Register (GPIO_DATA_DIR) General Purpose I/O Configuration Register Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 192. General Purpose I/O Data & Direction Register (GPIO_CFG)) Section 13.3, "LED Operation"...
Page 163: Gpio Ieee 1588 Timestamping
13.2.2 GPIO Interrupts Each GPIO of the LAN9312 provides the ability to trigger a unique GPIO interrupt in the Purpose I/O Interrupt Status and Enable Register bits of this register provides the current status of the corresponding interrupt, and each interrupt is enabled by setting the corresponding GPIO_INT_EN[11:0] bit.
Page 164: Ieee 1588 Gpio Interrupts
(GPIO2) Port 1 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface General Purpose I/O Interrupt Status and Enable 1588 Interrupt Status and Enable Register 1588 Interrupt Status and Enable Register (LED_CFG). These bits allow the configuration of each LED pin to indicate...
Page 165 The various LED indication functions shown in TX Port 0 - The signal is pulsed low for 80mS to indicate activity from the switch fabric to the Host MAC. This signal is then driven high for a minimum of 80mS, after which the process will repeat if TX activity is again detected.
Page 166: Chapter 14 Register Descriptions
Section 14.5, "Switch Fabric Control and Status Registers," on page 307 Figure 14.1 contains an overall base register memory map of the LAN9312. This memory map is not drawn to scale, and should be used for general reference only. Note: Register bit type definitions are provided in Note: Not all LAN9312 registers are memory mapped or directly addressable.
Page 167: Tx/Rx Fifo Ports
Direct FIFO Access Mode When the FIFO_SEL pin is driven high, the LAN9312 enters the direct FIFO access mode. In this mode, all host write operations are to the TX Data FIFO and all host read operations are from the RX Data FIFO.
Page 168: System Control And Status Registers
GPT_CFG 090h GPT_CNT 094h - 098h RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Chip ID and Revision Register, Interrupt Configuration Register, Interrupt Status Register, Interrupt Enable Register, Reserved for Future Use...
Page 169 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL 09Ch FREE_RUN 0A0h RX_DROP 0A4h MAC_CSR_CMD 0A4h PMI_DATA EEPROM Loader Access Only 0A8h MAC_CSR_DATA 0A8h...
Page 170 198h 1588_INT_STS_EN 19Ch 1588_CMD Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Port 2 1588 Source UUID Low-DWORD Transmit Capture Register, Section 14.2.5.8 Port 0 1588 Clock High-DWORD Receive Capture Register, Section 14.2.5.1...
Page 171 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.1 System Control and Status Registers (continued) ADDRESS OFFSET SYMBOL 1A0h MANUAL_FC_1 1A4h MANUAL_FC_2 1A8h MANUAL_FC_MII 1ACh SWITCH_CSR_DATA 1B0h SWITCH_CSR_CMD 1B4h E2P_CMD 1B8h E2P_DATA 1BCh...
Page 172: Interrupts
14.2.1 Interrupts This section details the interrupt related System CSR’s. These registers control, configure, and monitor the IRQ interrupt output pin and the various LAN9312 interrupt sources. For more information on the LAN9312 interrupts, refer to 14.2.1.1 Interrupt Configuration Register (IRQ_CFG) Offset: This read/write register configures and indicates the state of the IRQ signal.
Page 173 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS IRQ Polarity (IRQ_POL) When cleared, this bit enables the IRQ line to function as an active low output. When set, the IRQ output is active high. When the IRQ is configured as an open-drain output (via the IRQ_TYPE bit), this bit is ignored, and the interrupt is always active low.
Page 174: Interrupt Status Register (Int_Sts)
Register (INT_EN) is set high. Writing a one clears this interrupt. Device Ready (READY) This interrupt indicates that the LAN9312 is ready to be accessed after a power-up or reset condition. 1588 Interrupt Event (1588_EVNT) This bit indicates an interrupt event from the IEEE 1588 module. This bit...
Page 175 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS GP Timer (GPT_INT) This interrupt is issued when the (GPT_CNT) wraps past zero to FFFFh. RESERVED Power Management Interrupt Event (PME_INT) This interrupt is issued when a Power Management Event is detected as...
Page 176 This interrupt is generated when the RX Status FIFO reaches the programmed level in the Register (FIFO_INT). RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION RX Status Level field of the FIFO Level Interrupt DATASHEET...
Page 177: Interrupt Enable Register (Int_En)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.1.3 Interrupt Enable Register (INT_EN) Offset: This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of SW_INT_EN).
Page 178 RESERVED - This bit must be written with 0b for proper operation. RX Status FIFO Full Interrupt Enable (RSFF_EN) RX Status FIFO Level Interrupt Enable (RSFL_EN) RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet TYPE...
Page 179: Fifo Level Interrupt Register (Fifo_Int)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.1.4 FIFO Level Interrupt Register (FIFO_INT) Offset: This read/write register configures the limits where the RX/TX Data and Status FIFO’s will generate system interrupts. BITS 31:24...
Page 180: Host Mac & Fifo's
RX End Alignment (RX_EA) This field specifies the alignment that must be maintained on the last data transfer of a buffer. The LAN9312 will add extra DWORD’s of data up to the alignment specified in the table below. The host is responsible for removing these extra DWORD’s.
Page 181 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS 14:13 RESERVED 12:8 RX Data Offset (RXDOFF) This field controls the offset value, in bytes, that is added to the beginning of an RX data packet. The start of the valid data will be shifted by the number of bytes specified in this field.
Page 182: Transmit Configuration Register (Tx_Cfg)
When the transmitter has stopped this bit will clear. All writes to this bit are ignored while this bit is high. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 070h Size:...
Page 183: Receive Datapath Control Register (Rx_Dp_Ctrl)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.2.3 Receive Datapath Control Register (RX_DP_CTRL) Offset: This register is used to discard unwanted receive frames. BITS RX Data FIFO Fast Forward (RX_FFWD) Writing a 1 to this bit causes the RX Data FIFO to fast-forward to the start of the next frame.
Page 184: Rx Fifo Information Register (Rx_Fifo_Inf)
In cases where the payload does not end on a DWORD boundary, the total will be rounded up to the nearest DWORD. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 07Ch Size:...
Page 185: Tx Fifo Information Register (Tx_Fifo_Inf)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.2.5 TX FIFO Information Register (TX_FIFO_INF) Offset: This register contains the indication of free space in the TX Data FIFO and the used space in the TX Status FIFO.
Page 186: Host Mac Rx Dropped Frames Counter Register (Rx_Drop)
The interrupt RXDFH_INT (bit 23 of the (INT_STS)) can be issued when this counter passes through its halfway point (7FFFFFFFh to 80000000h). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 0A0h Size: 32 bits...
Page 187: Host Mac Csr Interface Command Register (Mac_Csr_Cmd)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.2.7 Host MAC CSR Interface Command Register (MAC_CSR_CMD) Offset: This read-write register is used to control the read and write operations to/from the Host MAC. This register in used in conjunction with the indirectly access the Host MAC CSR’s.
Page 188: Host Mac Csr Interface Data Register (Mac_Csr_Data)
The MAC_CSR_CMD and MAC_CSR_DATA registers must not be modified until the CSR Busy bit is cleared in the MAC_CSR_CMD register. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 0A8h Size: Host MAC CSR Interface Command Register Section 14.3, "Host MAC Control and Status...
Page 189: Host Mac Automatic Flow Control Configuration Register (Afc_Cfg)
Pause frames and backpressure are sent to the switch fabric to stop it from sending packets to the Host MAC. Network data into the switch fabric is affected only if the switch fabric buffering fills. Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is disabled.
Page 190: Table 14.2 Backpressure Duration Bit Mapping
Setting this bit overrides bits [3:1] of this register. Table 14.2 Backpressure Duration Bit Mapping [7:4] Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION BACKPRESSURE DURATION 100Mbs Mode 10uS...
Page 191 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.2 Backpressure Duration Bit Mapping (continued) SMSC LAN9312 BACKPRESSURE DURATION 250uS 300uS 350uS 400uS 450uS 500uS 550uS 600uS DATASHEET 252.2uS 302.2uS 352.2uS 402.2uS 452.2uS 502.2uS 552.2uS...
Page 192: Gpio/Led
0: 1588 clock event output active low 1: 1588 clock event output active high Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1E0h Size: DESCRIPTION 1588 Interrupt Status and Enable Register General (GPIO_INT_STS_EN).
Page 193 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS GPIO 8 Clock Event Polarity (GPIO_EVENT_POL_8) This bit determines if the 1588 clock event output on GPIO 8 is active high or low. 0: 1588 clock event output active low...
Page 194: General Purpose I/O Data & Direction Register (Gpio_Data_Dir)
For GPIOs 9 and 8, the pin direction is determined by the GPDIR bits and the 1588_GPIO_OE bits in the Configuration Register (GPIO_CFG). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1E4h Size: 32 bits DESCRIPTION...
Page 195: General Purpose I/O Interrupt Status And Enable Register (Gpio_Int_Sts_En)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.3.3 General Purpose I/O Interrupt Status and Enable Register (GPIO_INT_STS_EN) Offset: This read/write register contains the GPIO interrupt status bits. Writing a 1 to any of the interrupt status bits acknowledges and clears the interrupt. If enabled, these interrupt bits are cascaded into bit 12 (GPIO) of the to any of the interrupt enable bits will enable the corresponding interrupt as a source.
Page 196: Led Configuration Register (Led_Cfg)
EEPROM Loader. Refer to Section 4.2.4, "Configuration Straps," on page 40 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1BCh Size: 32 bits DESCRIPTION 164.
Page 197: Eeprom
Datasheet 14.2.4 EEPROM This section details the EEPROM related System CSR’s. These registers should only be used if an EEPROM has been connected to the LAN9312. Refer to chapter EEPROM Controller," on page 137 of the EEPROM Controller (EPC). 14.2.4.1...
Page 198 The READY bit in the Hardware Configuration Register (HW_CFG) to determine then the RELOAD is complete. 27:19 RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION [28] Operation READ EWDS EWEN...
Page 199 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS EEPROM Loader Address Overflow (LOADER_OVERFLOW) This bit indicates that the EEPROM Loader tried to read past the end of the EEPROM address space. This indicates misconfigured EEPROM data.
Page 200: Eeprom Data Register (E2P_Data)
RESERVED EEPROM Data (EEPROM_DATA) This field contains the data read from or written to the EEPROM. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1B8h Size: 32 bits EEPROM Command Register (E2P_CMD)
Page 201: Ieee 1588
14.2.5 IEEE 1588 This section details the IEEE 1588 timestamp related registers. Each port of the LAN9312 has a 1588 timestamp block with 8 related registers, 4 for transmit capture and 4 for receive capture. These sets of registers are identical in functionality for each port, and thus their register descriptions have been consolidated.
Page 202: Port X 1588 Clock Low-Dword Receive Capture Register (1588_Clock_Lo_Rx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 203: Port X 1588 Sequence Id, Source Uuid High-Word Receive Capture Register (1588_Seq_Id_Src_Uuid_Hi_Rx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 204: Port X 1588 Source Uuid Low-Dword Receive Capture Register (1588_Src_Uuid_Lo_Rx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 205: Port X 1588 Clock High-Dword Transmit Capture Register (1588_Clock_Hi_Tx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 206: Port X 1588 Clock Low-Dword Transmit Capture Register (1588_Clock_Lo_Tx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 207: Port X 1588 Sequence Id, Source Uuid High-Word Transmit Capture Register (1588_Seq_Id_Src_Uuid_Hi_Tx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 208: Port X 1588 Source Uuid Low-Dword Transmit Capture Register (1588_Src_Uuid_Lo_Tx_Capture_X)
Note: The selection between Sync or Delay_Req packets is based on the corresponding master/slave bit in the Note: There are multiple instantiations of this register, one for each port of the LAN9312. Refer to Section 14.2.5 Note: For Port 0(Host MAC), receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 209: Gpio 8 1588 Clock High-Dword Capture Register (1588_Clock_Hi_Capture_Gpio_8)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8) Offset: This read only register combined with the (1588_CLOCK_LO_CAPTURE_GPIO_8) BITS 31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO...
Page 210: Gpio 8 1588 Clock Low-Dword Capture Register (1588_Clock_Lo_Capture_Gpio_8)
31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 164h Size: 32 bits GPIO 8 1588 Clock High-DWORD Capture Register form the 64-bit GPIO 8 timestamp capture.
Page 211: Gpio 9 1588 Clock High-Dword Capture Register (1588_Clock_Hi_Capture_Gpio_9)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9) Offset: This read only register combined with the (1588_CLOCK_LO_CAPTURE_GPIO_9) BITS 31:0 Timestamp High (TS_HI) This field contains the high 32-bits of the timestamp upon activation of GPIO...
Page 212: Gpio 9 1588 Clock Low-Dword Capture Register (1588_Clock_Lo_Capture_Gpio_9)
31:0 Timestamp Low (TS_LO) This field contains the low 32-bits of the timestamp upon activation of GPIO Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 16Ch Size: 32 bits GPIO 9 1588 Clock High-DWORD Capture Register form the 64-bit GPIO 9 timestamp capture.
Page 213: 1588 Clock High-Dword Register (1588_Clock_Hi)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI) Offset: This read/write register combined with 64-bit 1588 Clock value. The 1588 Clock value is used for all 1588 timestamping. The 1588 Clock has...
Page 214: 1588 Clock Low-Dword Register (1588_Clock_Lo)
Note: The value read is the saved value of the 1588 Clock when the 1588_CLOCK_SNAPSHOT bit in the 1588 Command Register (1588_CMD) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 174h Size: 32 bits 1588 Clock High-DWORD Register (1588_CLOCK_HI) accordingly.
Page 215: 1588 Clock Addend Register (1588_Clock_Addend)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND) Offset: This read/write register is responsible for adjusting the 64-bit 1588 Clock frequency. Refer to Chapter 11, "IEEE 1588 Hardware Time Stamp Unit," on page 154 this register.
Page 216: 1588 Clock Target High-Dword Register (1588_Clock_Target_Hi)
(1588_CLOCK_TARGET_LO) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 17Ch Size: 1 5 8 8 C l o c k Ta r g e t L o w - D W O R D R e g i s t e r form the 64-bit 1588 Clock Target value.
Page 217: 1588 Clock Target Low-Dword Register (1588_Clock_Target_Lo)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) Offset: T h i s r e a d / w r i t e r e g i s t e r c o m b i n e d w i t h (1588_CLOCK_TARGET_HI) compared to the current 1588 Clock value and can be used to trigger an interrupt upon at match.
Page 218: 1588 Clock Target Reload High-Dword Register (1588_Clock_Target_Reload_Hi)
1588 Clock Compare value. Note: Both this register and the (1588_CLOCK_TARGET_RELOAD_LO) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 184h Size: 32 bits 1588 Clock Target Reload/Add Low-DWORD Register form the 64-bit 1588 Clock Target Reload value.
Page 219: 1588 Clock Target Reload/Add Low-Dword Register (1588_Clock_Target_Reload_Lo)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO) Offset: This read/write register combined with (1588_CLOCK_TARGET_RELOAD_HI) Clock Target Reload is the value that is reloaded or added to the 1588 Clock Compare value when a clock compare event occurs.
Page 220: 1588 Auxiliary Mac Address High-Word Register (1588_Aux_Mac_Hi)
1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) Offset: This read/write register combined with the (1588_AUX_MAC_LO) address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register Hardware Time Stamp Unit," on page 154...
Page 221: 1588 Auxiliary Mac Address Low-Dword Register (1588_Aux_Mac_Lo)
1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) Offset: This read/write register combined with the (1588_AUX_MAC_HI) address can be enabled for each port of the LAN9312 via their respective User Defined MAC Address Enable bit in the 1588 Configuration Register Hardware Time Stamp Unit," on page 154...
Page 222: 1588 Configuration Register (1588_Config)
Port 2 is already set due to a previous capture. 0: Disables TX Port 2 Lock 1: Enables TX Port 2 Lock Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 194h Size: 32 bits...
Page 223 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS Master/Slave Port 1 (M_nS_1) When set, Port 1 is a time clock master and captures timestamps when a Sync packet is transmitted and when a Delay_Req is received. When cleared, Port 1 is a time clock slave and captures timestamps when a Delay_Req packet is transmitted and when a Sync packet is received.
Page 224 0: Disables RX Port 0 Lock 1: Enables RX Port 0 Lock Note: For Port 0, receive is defined as data from the switch fabric, while transmit is to the switch fabric. Lock Enable TX Port 0(Host MAC) (LOCK_TX_MII) This bit enables/disables the TX lock. This lock prevents a 1588 capture from overwriting the Clock, UUDI and Sequence ID values if the 1588 TX interrupt for Port 0 is ready set due to a previous capture.
Page 225 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS Lock Enable GPIO 8 (LOCK_GPIO_8) This bit enables/disables the GPIO 8 lock. This lock prevents a 1588 capture from overwriting the Clock value if the 1588_GPIO8 interrupt in the Interrupt Status and Enable Register (1588_INT_STS_EN) due to a previous capture.
Page 226: 1588 Interrupt Status And Enable Register (1588_Int_Sts_En)
PTP packet and the 1588 clock was captured. 1588 Port 0(Host MAC) RX Interrupt (1588_MII_RX_INT) This interrupt indicates that a packet from the switch fabric to the Host MAC the matches the configured PTP packet and the 1588 clock was captured.
Page 227 Datasheet BITS 1588 Port 0(Host MAC) TX Interrupt (1588_MII_TX_INT) This interrupt indicates that a packet from the Host MAC to the switch fabric matches the configured PTP packet and the 1588 clock was captured. Note: For Port 0, receive is defined as data from the switch fabric, while transmit is to the switch fabric.
Page 228: 1588 Command Register (1588_Cmd)
1588 Clock Low-DWORD Register (1588_CLOCK_LO) values to be saved so they can be read. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 19Ch Size: 1588 Clock High-DWORD Register 1588 Clock Low-DWORD Register for additional information.
Page 229: Switch Fabric
This section details the memory mapped System CSR’s which are related to the Switch Fabric. The flow control of all three ports of the switch fabric can be configured via the memory mapped System CSR’s MANUAL_FC_1, MANUAL_FC_2 and MANUAL_FC_MII. The MAC address used by the switch for Pause frames is configured via the SWITCH_MAC_ADDRH and SWITCH_MAC_ADDRL registers.
Page 230 Once the EEPROM Loader re-writes the values, this register is updated with the new values. See Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION for additional information. Section 4.2.4, "Configuration Straps," on page 40...
Page 231: Port 2 Manual Flow Control Register (Manual_Fc_2)
Port 2 Manual Flow Control Register (MANUAL_FC_2) Offset: This read/write register allows for the manual configuration of the switch Port 2 flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated. Refer to information.
Page 232 Once the EEPROM Loader re-writes the values, this register is updated with the new values. See Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for additional information. Section 4.2.4, "Configuration Straps," on page 40...
Page 233: Port 0(Host Mac) Manual Flow Control Register (Manual_Fc_Mii)
Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) Offset: This read/write register allows for the manual configuration of the switch Port 0(Host MAC) flow control. This register also provides read back of the currently enabled flow control settings, whether set manually or Auto-Negotiated.
Page 234 Loader. Once the EEPROM Loader re-writes the value, this register is updated with the new values. See Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION for more information. for additional information.
Page 235: Switch Fabric Csr Interface Data Register (Switch_Csr_Data)
Upon a read, the value returned depends on the R/nW bit in the Fabric CSR Interface Command Register set, the data is from the switch fabric. If R/nW is cleared, the data is the value that was last written into this register.
Page 236: Switch Fabric Csr Interface Command Register (Switch_Csr_Cmd)
1: Enable Auto Decrement 27:20 RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1B0h Size: Switch Fabric CSR Interface Data Register to control the read and write operations to the various Switch Fabric CSR’s.
Page 237 15:0 CSR Address (CSR_ADDR[15:0]) This field selects the 16-bit address of the Switch Fabric CSR that will be accessed with a read or write operation. Refer to Accessible Switch Control and Status Registers,” on page 307 Switch Fabric CSR addresses.
Page 238: Switch Fabric Mac Address High Register (Switch_Mac_Addrh)
Offset: This register contains the upper 16-bits of the MAC address used by the switch for Pause frames. This r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h (SWITCH_MAC_ADDRL).
Page 239: Switch Fabric Mac Address Low Register (Switch_Mac_Addrl)
Offset: This register contains the lower 32-bits of the MAC address used by the switch for Pause frames. This r e g i s t e r i s u s e d i n c o n j u n c t i o n w i t h (SWITCH_MAC_ADDRH).
Page 240: Switch Fabric Csr Interface Direct Data Register (Switch_Csr_Direct_Data)
Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) Offset: This write-only register set is used to perform directly addressed write operations to the Switch Fabric CSR’s. Using this set of registers, writes can be directly addressed to select Switch Fabric registers,...
Page 241 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.3 Switch Fabric CSR to SWITCH_CSR_DIRECT_DATA Address Range Map (continued) REGISTER NAME MAC_TX_CFG_2 MAC_TX_FC_SETTINGS_2 MAC_IMR_2 SWE_ALR_CMD SWE_ALR_WR_DAT_0 SWE_ALR_WR_DAT_1 SWE_ALR_CFG SWE_VLAN_CMD SWE_VLAN_WR_DATA SWE_DIFFSERV_TBL_CMD SWE_DIFFSERV_TBL_WR_DATA SWE_GLB_INGRESS_CFG SWE_PORT_INGRESS_CFG...
Page 242 BM_EGRSS_RATE_00_01 BM_EGRSS_RATE_02_03 BM_EGRSS_RATE_10_11 BM_EGRSS_RATE_12_13 BM_EGRSS_RATE_20_21 BM_EGRSS_RATE_22_23 BM_VLAN_MII BM_VLAN_1 BM_VLAN_2 BM_IMR Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface SWITCH FABRIC CSR REGISTER # 1C03h 1C04h 1C09h 1C0Ah 1C0Ch 1C0Dh 1C0Eh 1C0Fh 1C10h...
Page 243: Phy Management Interface (Pmi)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.7 PHY Management Interface (PMI) The PMI registers are used (by the EEPROM Loader only) to indirectly access the PHY registers. Refer to Section 14.4, "Ethernet PHY Control and Status Registers," on page 285 information on the PHY registers.
Page 244: Phy Management Interface Access Register (Pmi_Access)
RESERVED RESERVED Note: This bit must always be written with a value of 1. RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 0A8h Size: 32 bits EEPROM Loader Access Only for additional information.
Page 245: Virtual Phy
All functionality and bit definitions comply with these standards. The IEEE 802.3 specified register index (in decimal) is included under the LAN9312 memory mapped offset of each Virtual PHY register as a reference. For additional information, refer to the IEEE 802.3 Specification.
Page 246: Virtual Phy Basic Control Register (Vphy_Basic_Ctrl)
1: Reset Loopback (VPHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions from the Host MAC are not sent to the switch fabric. Instead, they are looped back onto the receive path. 0: Loopback mode disabled (normal operation) 1: Loopback mode enabled...
Page 247 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS Collision Test (VPHY_COL_TEST) This bit enables/disables the collision test mode. When set, the collision signal to the Host MAC is active during transmission from the Host MAC.
Page 248: Virtual Phy Basic Status Register (Vphy_Basic_Status)
IEEE 802.3 clause 22.2.4). 0: No extended status information in Register 15 1: Extended status information in Register 15 RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C4h Size: 32 bits DESCRIPTION...
Page 249 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS MF Preamble Suppression This bit indicates whether the Virtual PHY accepts management frames with the preamble suppressed. 0: Management frames with preamble suppressed not accepted...
Page 250: Virtual Phy Identification Msb Register (Vphy_Id_Msb)
16-bits wide. Note 14.24 IEEE allows a value of zero in each of the 32-bits of the PHY Identifier. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C8h Size: 32 bits...
Page 251: Virtual Phy Identification Lsb Register (Vphy_Id_Lsb)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB) Offset: Index (decimal): This read/write register contains the LSB of the Virtual PHY Organizationally Unique Identifier (OUI). The MSB of the Virtual PHY OUI is contained in the (VPHY_ID_MSB).
Page 252: Virtual Phy Auto-Negotiation Advertisement Register (Vphy_An_Adv)
This bit determines the advertised 10BASE-T full duplex capability. 0: 10BASE-T full duplex ability not advertised 1: 10BASE-T full duplex ability advertised Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1D0h Size: 32 bits Section 10.2.4, "EEPROM Loader,"...
Page 253 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS 10BASE-T Half Duplex This bit determines the advertised 10BASE-T half duplex capability. 0: 10BASE-T half duplex ability not advertised 1: 10BASE-T half duplex ability advertised Selector Field This field identifies the type of message being sent by Auto-Negotiation.
Page 254: Virtual Phy Auto-Negotiation Link Partner Base Page Ability Register (Vphy_An_Lp_Base_Ability)
This bit indicates the emulated link partner PHY 100BASE-X full duplex capability. 0: 100BASE-X full duplex ability not supported 1: 100BASE-X full duplex ability supported Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1D4h Size: 32 bits DESCRIPTION...
Page 255: Table 14.5 Emulated Link Partner Pause Flow Control Ability Default Values
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS 100BASE-X Half Duplex This bit indicates the emulated link partner PHY 100BASE-X half duplex capability. 0: 100BASE-X half duplex ability not supported 1: 100BASE-X half duplex ability supported...
Page 256: Virtual Phy Auto-Negotiation Expansion Register (Vphy_An_Exp)
Note 14.41 The emulated link partner will show Auto-Negotiation able unless Auto-Negotiation fails (no common bits between the advertised ability and the link partner ability). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1D8h Size:...
Page 257: Virtual Phy Special Control/Status Register (Vphy_Special_Control_Status)
Switch Looopback MII When set, transmissions from the switch fabric Port 0(Host MAC) are not sent to the Host MAC. Instead, they are looped back into the switch engine. From the MAC viewpoint, this is effectively a FAR LOOPBACK. If loopback is enabled during half-duplex operation, then the Enable Receive...
Page 258 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface b i t o f t h e V i r t u a l P H Y B a s i c C o n t r o l R e g i s t e r is set.
Page 259: Miscellaneous
Miscellaneous This section details the remainder of the System CSR’s. These registers allow for monitoring and configuration of various LAN9312 functions such as the Chip ID/revision, byte order testing, power management, hardware configuration, general purpose timer, and free running counter.
Page 260: Byte Order Test Register (Byte_Test)
99 for additional information on byte ordering. Note: This register can be read while the LAN9312 is in the reset or not ready states. The BYTE_TEST register can optionally be used as a dummy read register when assuring minimum write-to-read or read-to-read timing.
Page 261: Hardware Configuration Register (Hw_Cfg)
MAC transmit threshold properties, and software reset. A detailed explanation of the allowable settings for FIFO memory allocation can be found in on page 121. Note: This register can be polled while the LAN9312 is in the reset or not ready state (READY bit is cleared). BITS 31:28...
Page 262 Note 14.48 The default value of this field is determined by the configuration strap auto_mdix_strap_1. Section 4.2.4, "Configuration Straps," on page 40 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION Section 9.7.3, "FIFO for more information.
Page 263: Power Management Control Register (Pmt_Ctrl)
Offset: This read-write register controls the power management features and the PME pin of the LAN9312. The ready state of the LAN9312 can be determined via the Device Ready (READY) bit of this register. Refer to Section 4.3, "Power Management," on page 46...
Page 264 1: PME pin enabled Device Ready (READY) When set, this bit indicates that the LAN9312 is ready to be accessed. Upon power-up, nRST reset, soft reset, or digital reset, the host processor may interrogate this field as an indication that the LAN9312 has stabilized and is fully active.
Page 265: General Purpose Timer Configuration Register (Gpt_Cfg)
General Purpose Timer Configuration Register (GPT_CFG) Offset: This read/write register configures the LAN9312 General Purpose Timer (GPT). The GPT can be configured to generate host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the 12.1, "General Purpose Timer,"...
Page 266: General Purpose Timer Count Register (Gpt_Cnt)
15:0 General Purpose Timer Current Count (GPT_CNT) This 16-bit field represents the current value of the GPT. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 090h Size: 32 bits General Purpose Timer Configuration Register (GPT_CFG) Section 12.1, "General Purpose Timer,"...
Page 267: Free Running 25Mhz Counter Register (Free_Run)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN) Offset: This read-only register reflects the current value of the free-running 25MHz counter. Refer to 12.2, "Free-Running Clock," on page 161...
Page 268: Reset Control Register (Reset_Ctl)
14.2.9.8 Reset Control Register (RESET_CTL) Offset: This register contains software controlled resets. Note: This register can be read while the LAN9312 is in the reset or not ready states. BITS 31:4 RESERVED Virtual PHY Reset (VPHY_RST) Setting this bit resets the Virtual PHY. When the Virtual PHY is released from reset, this bit is automatically cleared.
Page 269: Host Mac Control And Status Registers
MAC address, flow control, multicast hash table, and wake-up configuration. The Host MAC CSR’s also provide serial access to the PHYs via the registers HMAC_MII_ACC and HMAC_MII_DATA. These registers allow access to the 10/100 Ethernet PHY registers and the switch engine (via Port 0). Table 14.6 Host MAC Adressable Registers...
Page 270: Host Mac Control Register (Hmac_Cr)
This read/write register establishes the RX and TX operation modes and controls for address filtering and packet filtering. Refer to Bits 19-15, 13, and 11 determine if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine which packets get sent to the Host MAC.
Page 271 9.4.2, "Hash Only Filtering," on page 115 RESERVED Hash/Perfect Filtering Mode (HPFILT) When cleared (0), the LAN9312 will implement a perfect address filter on incoming frames according the address specified in the Host MAC address registers (Host MAC Address High Register (HMAC_ADDRH)
Page 272 When set, the Host MAC’s receiver is enabled and will receive frames. When cleared, the MAC’s receiver is disabled and will not receive any frames. RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION # Bits Used from LFSR Counter DATASHEET Datasheet...
Page 273: Host Mac Address High Register (Hmac_Addrh)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.3.2 Host MAC Address High Register (HMAC_ADDRH) Offset: This read/write register contains the upper 16-bits of the physical address of the Host MAC. The contents of this register are optionally loaded from the EEPROM at power-on through the EEPROM Loader if a programmed EEPROM is detected.
Page 274: Host Mac Address Low Register (Hmac_Addrl)
EEPROM at power-on. The host can update the contents of this field after the initialization process has completed. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 32 bits Section 9.6, "Host MAC Address," on page 119 Section 10.2, "I2C/Microwire Master EEPROM Controller,"...
Page 275: Host Mac Multicast Hash Table High Register (Hmac_Hashh)
Hash Table Low register contains the lower 32 bits of the hash table. Refer to Filtering," on page 114 This table determines if the Host MAC accepts the packets from the switch fabric. The switch fabric address table and configuration determine the packets that get sent to the Host MAC.
Page 276: Host Mac Multicast Hash Table Low Register (Hmac_Hashl)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL) Offset: Size: 32 bits This read/write register defines the lower 32-bits of the Multicast Hash Table. Please refer to the...
Page 277: Host Mac Mii Access Register (Hmac_Mii_Acc)
Host MAC MII Data Register The LAN driver software must set this bit in order for the LAN9312 to read or write any of the MII PHY registers. During a MII register access, this bit will be set, signifying a read or write access is in progress.
Page 278: Host Mac Mii Data Register (Hmac_Mii_Data)
This field contains the 16-bit value read from the PHY read operation or the 16-bit data value to be written to the PHY before an MII write operation. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 32 bits...
Page 279: Host Mac Flow Control Register (Hmac_Flow)
System CSR’s to configure flow control. Software flow control is initiated using the AFC_CFG register. Note: The Host MAC will not transmit pause frames or assert back pressure if the transmitter is disabled. Note: For the Host MAC, flow control/backpressure is to/from the switch fabric, not the external network. BITS 31:16...
Page 280 Notes: When writing this register, the FCBSY bit must always be zero. Applications must always write a zero to this bit Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet...
Page 281: Host Mac Vlan1 Tag Register (Hmac_Vlan1)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) Offset: This read/write register contains the VLAN tag field to identify VLAN1 frames. When a VLAN1 frame is detected, the legal frame length is increased from 1518 bytes to 1522 bytes. Refer to "Virtual Local Area Network (VLAN) Support,"...
Page 282: Host Mac Vlan2 Tag Register (Hmac_Vlan2)
If both are set to the same value, VLAN1 is given higher precedence and the maximum legal frame length is set to 1522. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 32 bits for additional information.
Page 283: Host Mac Wake-Up Frame Filter Register (Hmac_Wuff)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF) Offset: This write-only register is used to configure the wake-up frame filter. Refer to Frame Detection," on page 116...
Page 284: Host Mac Wake-Up Control And Status Register (Hmac_Wucsr)
Magic Packet Enable (MPEN) When set, Magic Packet Wake-up mode is enabled. RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: Host MAC Wake-up Frame Filter Register for additional information. DESCRIPTION...
Page 285: Ethernet Phy Control And Status Registers
14.4 Ethernet PHY Control and Status Registers This section details the various LAN9312 Ethernet PHY control and status registers. The LAN9312 contains three PHY’s: Port 1 PHY, Port 2 PHY and a Virtual PHY. All PHY registers follow the IEEE 802.3 (clause 22.2.4) specified MII management register set.
Page 286 PHY_INTERRUPT_SOURCE_x PHY_INTERRUPT_MASK_x PHY_SPECIAL_CONTROL_STATUS_x Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Port x PHY Mode Control/Status Register, Port x PHY Special Modes Register, Port x PHY Special Control/Status Indication Register, Section 14.4.2.10...
Page 287: Port X Phy Basic Control Register (Phy_Basic_Control_X)
1: Reset Loopback (PHY_LOOPBACK) This bit enables/disables the loopback mode. When enabled, transmissions from the switch fabric are not sent to network. Instead, they are looped back into the switch fabric. Note: If loopback is enabled during half-duplex operation, then the...
Page 288 Refer to Straps," on page 40 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION Auto-Negotiation (PHY_AN) Section 4.2.4, "Configuration Straps," on for more information.
Page 289: Port X Phy Basic Status Register (Phy_Basic_Status_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.4.2.2 Port x PHY Basic Status Register (PHY_BASIC_STATUS_x) Index (decimal): 1 This register is used to monitor the status of the Port x PHY. BITS 100BASE-T4 This bit displays the status of 100BASE-T4 compatibility.
Page 290 Note 14.52 The PHY supports 100BASE-TX (half and full duplex) and 10BASE-T (half and full duplex) only. All other modes will always return as 0 (unable to perform). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET...
Page 291: Port X Phy Identification Msb Register (Phy_Id_Msb_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.4.2.3 Port x PHY Identification MSB Register (PHY_ID_MSB_x) Index (decimal): 2 This read/write register contains the MSB of the Organizationally Unique Identifier (OUI) for the Port x PHY.
Page 292: Port X Phy Identification Lsb Register (Phy_Id_Lsb_X)
This field contains the 6-bit manufacturer’s model number of the PHY. Revision Number This field contain the 4-bit manufacturer’s revision number of the PHY. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 16 bits Port x PHY Identification MSB Register...
Page 293: Port X Phy Auto-Negotiation Advertisement Register (Phy_An_Adv_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.4.2.5 Port x PHY Auto-Negotiation Advertisement Register (PHY_AN_ADV_x) Index (decimal): 4 This read/write register contains the advertised ability of the Port x PHY and is used in the Auto- Negotiation process with the link partner.
Page 294: Table 14.8 10Base-T Full Duplex Advertisement Default Value
Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION 40. Refer to Section 4.2.4, "Configuration Straps," on page 40 Table 14.8 defines the default behavior of this bit.
Page 295 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.9 10BASE-T Half Duplex Advertisement Bit Default Value autoneg_strap_x speed_strap_x Default 10BASE-T Half Duplex (Bit 5) Value SMSC LAN9312 Revision 1.4 (08-19-08) DATASHEET...
Page 296: Port X Phy Auto-Negotiation Link Partner Base Page Ability Register (Phy_An_Lp_Base_Ability_X)
This bit indicates the link partner PHY 100BASE-X half duplex capability. 0: 100BASE-X half duplex ability not supported 1: 100BASE-X half duplex ability supported Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION...
Page 297 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS 10BASE-T Full Duplex This bit indicates the link partner PHY 10BASE-T full duplex capability. 0: 10BASE-T full duplex ability not supported 1: 10BASE-T full duplex ability supported 10BASE-T Half Duplex This bit indicates the link partner PHY 10BASE-T half duplex capability.
Page 298: Port X Phy Auto-Negotiation Expansion Register (Phy_An_Exp_X)
This bit indicates the Auto-negotiation ability of the link partner. 0: Link partner is not Auto-Negotiation able 1: Link partner is Auto-Negotiation able Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION...
Page 299: Port X Phy Mode Control/Status Register (Phy_Mode_Control_Status_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.4.2.8 Port x PHY Mode Control/Status Register (PHY_MODE_CONTROL_STATUS_x) Index (decimal): 17 This read/write register is used to control and monitor various Port x PHY configuration options.
Page 300: Port X Phy Special Modes Register (Phy_Special_Modes_X)
10BASE-T Full Duplex. Auto-negotiation disabled. 100BASE-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: Section 10.2.4, "EEPROM Loader," on page 149 DESCRIPTION Table 14.10...
Page 301 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.10 MODE[2:0] Definitions (continued) MODE[2:0] MODE DEFINITIONS 100BASE-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive. 100BASE-TX Half Duplex is advertised. Auto- negotiation enabled.
Page 302: Port X Phy Special Control/Status Indication Register (Phy_Special_Control_Stat_Ind_X)
R e s e t ( P H Y _ R S T ) (PHY_BASIC_CONTROL_x) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: DESCRIPTION for configuration strap Table 14.11.
Page 303: Table 14.11Auto-Mdix Enable And Auto-Mdix State Bit Functionality
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.11 Auto-MDIX Enable and Auto-MDIX State Bit Functionality Auto-MDIX Enable Auto-MDIX State (Bit 14) SMSC LAN9312 (Bit 13) Manual mode, no crossover Manual mode, crossover...
Page 304: Port X Phy Interrupt Source Flags Register (Phy_Interrupt_Source_X)
This interrupt source bit indicates an Auto-Negotiation page received. 0: Not source of interrupt 1: Auto-Negotiation page received RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 16 bits (PHY_INTERRUPT_MASK_x). DESCRIPTION...
Page 305: Port X Phy Interrupt Mask Register (Phy_Interrupt_Mask_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.4.2.12 Port x PHY Interrupt Mask Register (PHY_INTERRUPT_MASK_x) Index (decimal): 30 This read/write register is used to enable or mask the various Port x PHY interrupts and is used in...
Page 306: Port X Phy Special Control/Status Register (Phy_Special_Control_Status_X)
RESERVED 10BASE-T Half-duplex 100BASE-TX Half-duplex RESERVED RESERVED 10BASE-T Full-duplex 100BASE-TX Full-duplex RESERVED RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Size: 16 bits DESCRIPTION DESCRIPTION DATASHEET Datasheet TYPE DEFAULT 0000010b 000b...
Page 307: Switch Fabric Control And Status Registers
14.5 Switch Fabric Control and Status Registers This section details the various LAN9312 switch control and status registers that reside within the switch fabric. The switch control and status registers allow configuration of each individual switch port, the switch engine, and buffer manager. Switch fabric related interrupts and resets are also controlled and monitored via the switch CSRs.
Page 308 MAC_TX_PKTOK_CNT_MII 0454h MAC_TX_64_CNT_MII Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Port 0 MAC Receive 256 to 511 Byte Count Register, Section 14.5.2.7 Port 0 MAC Receive 512 to 1023 Byte Count Register, Section 14.5.2.8...
Page 309 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0455h MAC_TX_65_TO_127_CNT_MII 0456h MAC_TX_128_TO_255_CNT_MII 0457h MAC_TX_256_TO_511_CNT_MII 0458h MAC_TX_512_TO_1023_CNT_MII 0459h MAC_TX_1024_TO_MAX_CNT_MII 045Ah MAC_TX_UNDSZE_CNT_MII 045Bh...
Page 310 RESERVED 0851h MAC_TX_DEFER_CNT_1 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Port 1 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5 Port 1 MAC Receive 128 to 255 Byte Count Register, Section 14.5.2.6...
Page 311 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0852h MAC_TX_PAUSE_CNT_1 0853h MAC_TX_PKTOK_CNT_1 0854h MAC_RX_64_CNT_1 0855h MAC_TX_65_TO_127_CNT_1 0856h MAC_TX_128_TO_255_CNT_1 0857h MAC_TX_256_TO_511_CNT_1 0858h...
Page 312 0C40h MAC_TX_CFG_2 0C41h MAC_TX_FC_SETTINGS_2 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Port 2 MAC Receive Undersize Count Register, Section 14.5.2.3 Port 2 MAC Receive 64 Byte Count Register, Port 2 MAC Receive 65 to 127 Byte Count Register, Section 14.5.2.5...
Page 313 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 0C42h-0C50h RESERVED 0C51h MAC_TX_DEFER_CNT_2 0C52h MAC_TX_PAUSE_CNT_2 0C53h MAC_TX_PKTOK_CNT_2 0C54h MAC_RX_64_CNT_2 0C55h MAC_TX_65_TO_127_CNT_2 0C56h...
Page 314 1845h SWE_PRI_TO_QUE 1846h SWE_PORT_MIRROR Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Switch Engine CSRs Switch Engine ALR Command Register, Switch Engine ALR Write Data 0 Register, Switch Engine ALR Write Data 1 Register,...
Page 315 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1847h SWE_INGRESS_PORT_TYP 1848h SWE_BCST_THROT 1849h SWE_ADMT_N_MEMBER 184Ah SWE_INGRESS_RATE_CFG 184Bh SWE_INGRESS_RATE_CMD 184Ch SWE_INGRESS_RATE_CMD_STS 184Dh...
Page 316 BM_RATE_DRP_CNT_SRC_2 1C19 -1C1F RESERVED Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface REGISTER NAME Buffer Manager Flow Control Pause Level Register, Section 14.5.4.3 Buffer Manager Flow Control Resume Level Register, Section 14.5.4.4 Buffer Manager Broadcast Buffer Level Register, Section 14.5.4.5...
Page 317 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Table 14.12 Indirectly Accessible Switch Control and Status Registers (continued) REGISTER # SYMBOL 1C20h BM_IMR 1C21h BM_IPR 1C22 -FFFF RESERVED SMSC LAN9312 REGISTER NAME Buffer Manager Interrupt Mask Register,...
Page 318: General Switch Csrs
General Switch CSRs This section details the general switch fabric CSRs. These registers control the main reset and interrupt functions of the switch fabric. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.1.1...
Page 319: Switch Reset Register (Sw_Reset)
This register contains the switch fabric global reset. Refer to more information. BITS 31:1 RESERVED Switch Fabric Reset (SW_RESET) This bit is the global switch fabric reset. All switch fabric blocks are affected. This bit must be manually cleared. SMSC LAN9312 0001h Size: 32 bits Section 4.2, "Resets,"...
Page 320: Switch Global Interrupt Mask Register (Sw_Imr)
Switch Global Interrupt Mask Register (SW_IMR) Register #: This read/write register contains the global interrupt mask for the switch fabric interrupts. All switch related interrupts in the register. An interrupt is masked by setting the corresponding bit of this register. Clearing a bit will unmask the interrupt.
Page 321: Switch Global Interrupt Pending Register (Sw_Ipr)
Switch Global Interrupt Pending Register (SW_IPR) Register #: This read-only register contains the pending global interrupts for the switch fabric. A set bit indicates an unmasked bit in the corresponding switch fabric sub-system has been triggered. All switch related interrupts in this register may be masked via the register.
Page 322: Switch Port 0, Port 1, And Port 2 Csrs
Switch Port 0, Port 1, and Port 2 CSRs This section details the switch Port 0(Host MAC), Port 1, and Port 2 CSRs. Each port provides a functionally identical set of registers which allow for the configuration of port settings, interrupts, and the monitoring of the various packet counters.
Page 323: Port X Mac Receive Configuration Register (Mac_Rx_Cfg_X)
This bit must always be written as 0. RESERVED Enable Receive Own Transmit When set, the switch port will receive its own transmission if it is looped back from the PHY. Normally, this function is only used in Half Duplex PHY loopback.
Page 324: Port X Mac Receive Undersize Count Register (Mac_Rx_Undsze_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 115 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0410h Size: 32 bits...
Page 325: Port X Mac Receive 64 Byte Count Register (Mac_Rx_64_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.4 Port x MAC Receive 64 Byte Count Register (MAC_RX_64_CNT_x) Register #: This register provides a counter of 64 byte packets received by the port. The counter is cleared upon being read.
Page 326: Port X Mac Receive 65 To 127 Byte Count Register (Mac_Rx_65_To_127_Cnt_X)
Note: A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0412h Size:...
Page 327: Port X Mac Receive 128 To 255 Byte Count Register (Mac_Rx_128_To_255_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.6 Port x MAC Receive 128 to 255 Byte Count Register (MAC_RX_128_TO_255_CNT_x) Register #: This register provides a counter of received packets between the size of 128 to 255 bytes. The counter is cleared upon being read.
Page 328: Port X Mac Receive 256 To 511 Byte Count Register (Mac_Rx_256_To_511_Cnt_X)
Note: A bad packet is defined as a packet that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes is rounded down to the nearest byte. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0414h Size:...
Page 329: Port X Mac Receive 512 To 1023 Byte Count Register (Mac_Rx_512_To_1023_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.8 Port x MAC Receive 512 to 1023 Byte Count Register (MAC_RX_512_TO_1023_CNT_x) Register #: This register provides a counter of received packets between the size of 512 to 1023 bytes. The counter is cleared upon being read.
Page 330: Port X Mac Receive 1024 To Max Byte Count Register (Mac_Rx_1024_To_Max_Cnt_X)
(e.g. a 1518 1/2 byte packet) is counted. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0416h Size:...
Page 331: Port X Mac Receive Oversize Count Register (Mac_Rx_Ovrsze_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.10 Port x MAC Receive Oversize Count Register (MAC_RX_OVRSZE_CNT_x) Register #: This register provides a counter of received packets with a size greater than the maximum byte size.
Page 332: Port X Mac Receive Ok Count Register (Mac_Rx_Pktok_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0418h Size:...
Page 333: Port X Mac Receive Crc Error Count Register (Mac_Rx_Crcerr_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.12 Port x MAC Receive CRC Error Count Register (MAC_RX_CRCERR_CNT_x) Register #: This register provides a counter of received packets that with CRC errors. The counter is cleared upon being read.
Page 334: Port X Mac Receive Multicast Count Register (Mac_Rx_Mulcst_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 041Ah Size:...
Page 335: Port X Mac Receive Broadcast Count Register (Mac_Rx_Brdcst_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.14 Port x MAC Receive Broadcast Count Register (MAC_RX_BRDCST_CNT_x) Register #: This register provides a counter of valid received packets with a broadcast destination address. The counter is cleared upon being read.
Page 336: Port X Mac Receive Pause Frame Count Register (Mac_Rx_Pause_Cnt_X)
Minimum rollover time at 100Mbps is approximately 481 hours. Note: A bad packet is one that has a FCS or Symbol error. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 041Ch Size:...
Page 337: Port X Mac Receive Fragment Error Count Register (Mac_Rx_Frag_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.16 Port x MAC Receive Fragment Error Count Register (MAC_RX_FRAG_CNT_x) Register #: This register provides a counter of received packets of less than 64 bytes and a FCS error. The counter is cleared upon being read.
Page 338: Port X Mac Receive Jabber Error Count Register (Mac_Rx_Jabb_Cnt_X)
(e.g. a 1518 1/2 byte packet) and contains a FCS error is not considered jabber and is not counted here. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 041Eh Size:...
Page 339: Port X Mac Receive Alignment Error Count Register (Mac_Rx_Align_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.18 Port x MAC Receive Alignment Error Count Register (MAC_RX_ALIGN_CNT_x) Register #: This register provides a counter of received packets with 64 bytes to the maximum allowable, and a FCS error.
Page 340: Port X Mac Receive Packet Length Count Register (Mac_Rx_Pktlen_Cnt_X)
Note: A bad packet is one that has an FCS or Symbol error. For this counter, a packet that is not an integral number of bytes (e.g. a 1518 1/2 byte packet) is rounded down to the nearest byte. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0420h Size:...
Page 341: Port X Mac Receive Good Packet Length Count Register (Mac_Rx_Goodpktlen_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.20 Port x MAC Receive Good Packet Length Count Register (MAC_RX_GOODPKTLEN_CNT_x) Register #: This register provides a counter of total bytes received in good packets. The counter is cleared upon being read.
Page 342: Port X Mac Receive Symbol Error Count Register (Mac_Rx_Symbol_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 115 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0422h Size: 32 bits...
Page 343: Port X Mac Receive Control Frame Count Register (Mac_Rx_Ctlfrm_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.22 Port x MAC Receive Control Frame Count Register (MAC_RX_CTLFRM_CNT_x) Register #: This register provides a counter of good packets with a type field of 8808h. The counter is cleared upon being read.
Page 344: Port X Mac Transmit Configuration Register (Mac_Tx_Cfg_X)
TX Enable When set, the transmit port is enabled. When cleared, the transmit port is disabled. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0440h Size: 32 bits Port1: 0840h...
Page 345: Port X Mac Transmit Flow Control Settings Register (Mac_Tx_Fc_Settings_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.24 Port x MAC Transmit Flow Control Settings Register (MAC_TX_FC_SETTINGS_x) Register #: This read/write register configures the flow control settings of the port. BITS 31:18 RESERVED...
Page 346: Port X Mac Transmit Deferred Count Register (Mac_Tx_Defer_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0451h Size: 32 bits...
Page 347: Port X Mac Transmit Pause Count Register (Mac_Tx_Pause_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.26 Port x MAC Transmit Pause Count Register (MAC_TX_PAUSE_CNT_x) Register #: This register provides a counter of transmitted pause packets. The counter is cleared upon being read.
Page 348: Port X Mac Transmit Ok Count Register (Mac_Tx_Pktok_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0453h Size: 32 bits...
Page 349: Port X Mac Transmit 64 Byte Count Register (Mac_Tx_64_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.28 Port x MAC Transmit 64 Byte Count Register (MAC_TX_64_CNT_x) Register #: This register provides a counter of 64 byte packets transmitted by the port. The counter is cleared upon being read.
Page 350: Port X Mac Transmit 65 To 127 Byte Count Register (Mac_Tx_65_To_127_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 487 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0455h Size: 32 bits...
Page 351: Port X Mac Transmit 128 To 255 Byte Count Register (Mac_Tx_128_To_255_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.30 Port x MAC Transmit 128 to 255 Byte Count Register (MAC_TX_128_TO_255_CNT_x) Register #: This register provides a counter of transmitted packets between the size of 128 to 255 bytes. The counter is cleared upon being read.
Page 352: Port X Mac Transmit 256 To 511 Byte Count Register (Mac_Tx_256_To_511_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 1581 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0457h Size: 32 bits...
Page 353: Port X Mac Transmit 512 To 1023 Byte Count Register (Mac_Tx_512_To_1023_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.32 Port x MAC Transmit 512 to 1023 Byte Count Register (MAC_TX_512_TO_1023_CNT_x) Register #: This register provides a counter of transmitted packets between the size of 512 to 1023 bytes. The counter is cleared upon being read.
Page 354: Port X Mac Transmit 1024 To Max Byte Count Register (Mac_Tx_1024_To_Max_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 5979 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0459h Size: 32 bits...
Page 355: Port X Mac Transmit Undersize Count Register (Mac_Tx_Undsze_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.34 Port x MAC Transmit Undersize Count Register (MAC_TX_UNDSZE_CNT_x) Register #: This register provides a counter of undersized packets transmitted by the port. The counter is cleared upon being read.
Page 356: Port X Mac Transmit Packet Length Count Register (Mac_Tx_Pktlen_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 5.8 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 045Ch Size: 32 bits...
Page 357: Port X Mac Transmit Broadcast Count Register (Mac_Tx_Brdcst_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.36 Port x MAC Transmit Broadcast Count Register (MAC_TX_BRDCST_CNT_x) Register #: This register provides a counter of transmitted broadcast packets. The counter is cleared upon being read.
Page 358: Port X Mac Transmit Multicast Count Register (Mac_Tx_Mulcst_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 045Eh Size: 32 bits...
Page 359: Port X Mac Transmit Late Collision Count Register (Mac_Tx_Latecol_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.38 Port x MAC Transmit Late Collision Count Register (MAC_TX_LATECOL_CNT_x) Register #: This register provides a counter of transmitted packets which experienced a late collision. The counter is cleared upon being read.
Page 360: Port X Mac Transmit Excessive Collision Count Register (Mac_Tx_Exccol_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 1466 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0460h Size: 32 bits...
Page 361: Port X Mac Transmit Single Collision Count Register (Mac_Tx_Snglecol_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.40 Port x MAC Transmit Single Collision Count Register (MAC_TX_SNGLECOL_CNT_x) Register #: This register provides a counter of transmitted packets which experienced exactly 1 collision. The counter is cleared upon being read.
Page 362: Port X Mac Transmit Multiple Collision Count Register (Mac_Tx_Multicol_Cnt_X)
This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 664 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0462h Size: 32 bits...
Page 363: Port X Mac Transmit Total Collision Count Register (Mac_Tx_Totalcol_Cnt_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.42 Port x MAC Transmit Total Collision Count Register (MAC_TX_TOTALCOL_CNT_x) Register #: This register provides a counter of total collisions including late collisions. The counter is cleared upon being read.
Page 364: Port X Mac Interrupt Mask Register (Mac_Imr_X)
RESERVED RESERVED Note: These bits must be written as 11h Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Port0: 0480h Size: Port1: 0880h Port2: 0C80h may be masked via this register. An interrupt is masked by setting the for more information.
Page 365: Port X Mac Interrupt Pending Register (Mac_Ipr_X)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.2.44 Port x MAC Interrupt Pending Register (MAC_IPR_x) Register #: This read-only register contains the pending Port x interrupts. A set bit indicates an interrupt has been triggered.
Page 366: Switch Engine Csrs
This section details the switch engine related CSRs. These registers allow configuration and monitoring of the various switch engine components including the ALR, VLAN, Port VID, and DIFFSERV tables. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.3.1...
Page 367: Switch Engine Alr Write Data 0 Register (Swe_Alr_Wr_Dat_0)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.2 Switch Engine ALR Write Data 0 Register (SWE_ALR_WR_DAT_0) Register #: This register is used in conjunction with the (SWE_ALR_WR_DAT_1) Entry command in the BITS 31:0...
Page 368: Switch Engine Alr Write Data 1 Register (Swe_Alr_Wr_Dat_1)
Static bit of this register is set, and the DA Highest Priority (bit 5) in the Switch Engine Global Ingress Configuration Register (SWE_GLOBAL_INGRSS_CFG) Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1802h Size: Switch Engine ALR Write Data 0 Register...
Page 369 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS 18:16 Port These bits indicate the port(s) associated with this MAC address. When bit 18 is cleared, a single port is selected. When bit 18 is set, multiple ports are selected.
Page 370: Switch Engine Alr Read Data 0 Register (Swe_Alr_Rd_Dat_0)
32 bits of the MAC address. Bit 0 holds the LSB of the first byte (the multicast bit). Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1805h Size: Switch Engine ALR Read Data 1 Register to read the ALR table.
Page 371: Switch Engine Alr Read Data 1 Register (Swe_Alr_Rd_Dat_1)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.5 Switch Engine ALR Read Data 1 Register (SWE_ALR_RD_DAT_1) Register #: This register is used in conjunction with the (SWE_ALR_RD_DAT_0) loaded via the Get First Entry or Get Next Entry commands in the Register (SWE_ALR_CMD).
Page 372 (the last bit on the wire). The first 32 bits of the MAC address are located in the Switch Engine ALR Read Data 0 Register Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION ASSOCIATED PORT(S) Port 0(Host MAC)
Page 373: Switch Engine Alr Command Status Register (Swe_Alr_Cmd_Sts)
When set, indicates that the Make Entry command is taking place. This bit is cleared once the Make Entry command has finished. Note 14.62 The default value of this bit is 0 immediately following any switch fabric reset and then self- sets to 1 once the ALR table is initialized.
Page 374: Switch Engine Alr Configuration Register (Swe_Alr_Cfg)
31:1 RESERVED ALR Age Test When set, this bit decreases the aging timer from 5 minutes to 50mS. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1809h Size: 32 bits DESCRIPTION DATASHEET...
Page 375: Switch Engine Vlan Command Register (Swe_Vlan_Cmd)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.8 Switch Engine VLAN Command Register (SWE_VLAN_CMD) Register #: This register is used to read and write the VLAN or Port VID tables. A write to this address performs the specified access.
Page 376: Switch Engine Vlan Write Data Register (Swe_Vlan_Wr_Data)
VLAN entry. Note: A value of 3FFh is considered reserved by IEEE 802.1Q and should not be used. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 180Ch Size: DESCRIPTION Switch Engine...
Page 377: Switch Engine Vlan Read Data Register (Swe_Vlan_Rd_Data)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.10 Switch Engine VLAN Read Data Register (SWE_VLAN_RD_DATA) Register #: This register is used to read the VLAN or Port VID tables. BITS 31:18 RESERVED 17:0...
Page 378: Switch Engine Vlan Command Status Register (Swe_Vlan_Cmd_Sts)
When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1810h Size:...
Page 379: Switch Engine Diffserv Table Command Register (Swe_Diffserv_Tbl_Cfg)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.12 Switch Engine DIFFSERV Table Command Register (SWE_DIFFSERV_TBL_CFG) Register #: This register is used to read and write the DIFFSERV table. A write to this address performs the specified access.
Page 380: Switch Engine Diffserv Table Write Data Register (Swe_Diffserv_Tbl_Wr_Data)
DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS/CS field that matches this index. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1812h Size: 32 bits...
Page 381: Switch Engine Diffserv Table Read Data Register (Swe_Diffserv_Tbl_Rd_Data)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.14 Switch Engine DIFFSERV Table Read Data Register (SWE_DIFFSERV_TBL_RD_DATA) Register #: This register is used to read the DIFFSERV table. BITS 31:3 RESERVED DIFFSERV Priority These bits specify the assigned receive priority for IP packets with a ToS/CS field that matches this index.
Page 382: Switch Engine Diffserv Table Command Status Register (Swe_Diffserv_Tbl_Cmd_Sts)
When set, this bit indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1814h Size:...
Page 383: Switch Engine Global Ingress Configuration Register (Swe_Global_Ingrss_Cfg)
When set, IPv4 IGMP packets are snooped and sent to the MLD/IGMP snoop port. SWE Counter Test When this bit is set the Switch Engine counters that normally clear to 0 when read will be set to 7FFF_FFFCh when read. DA Highest Priority...
Page 384 When set, VLAN ingress rules are enabled. This also enables the VLAN to be used as the transmit priority queue selection. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet...
Page 385: Switch Engine Port Ingress Configuration Register (Swe_Port_Ingrss_Cfg)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.17 Switch Engine Port Ingress Configuration Register (SWE_PORT_INGRSS_CFG) Register #: This register is used to configure the per port ingress rules. BITS 31:6 RESERVED Enable Learning on Ingress...
Page 386: Switch Engine Admit Only Vlan Register (Swe_Admt_Only_Vlan)
The VLAN Enable bit in the Register (SWE_GLOBAL_INGRSS_CFG) have an affect. There is one enable bit per ingress port. Bits 2,1,0 correspond to switch ports 2,1,0 respectively. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface...
Page 387: Switch Engine Port State Register (Swe_Port_State)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.19 Switch Engine Port State Register (SWE_PORT_STATE) Register #: This register is used to configure the per port spanning tree state. BITS 31:6 RESERVED Port State Port 2 These bits specify the spanning tree port states for Port 2.
Page 388: Switch Engine Priority To Queue Register (Swe_Pri_To_Que)
Priority 0 traffic Class These bits specify the egress queue that is used for packets with a priority of 0. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1845h Size: 32 bits...
Page 389: Switch Engine Port Mirroring Register (Swe_Port_Mirror)
Bits 7,6,5 correspond to switch ports 2,1,0 respectively. Note: Only one port should be set as the sniffer. Mirrored Port These bits specify if a port is to be mirrored. Bits 4,3,2 correspond to switch ports 2,1,0 respectively. Note: Multiple ports can be set as mirrored.
Page 390: Switch Engine Ingress Port Type Register (Swe_Ingrss_Port_Typ)
A setting of 11b enables the usage of the VLAN tag to specify the packet destination. All other values disable this feature. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1847h Size:...
Page 391: Switch Engine Broadcast Throttling Register (Swe_Bcst_Throt)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.23 Switch Engine Broadcast Throttling Register (SWE_BCST_THROT) Register #: This register configures the broadcast input rate throttling. BITS 31:27 RESERVED Broadcast Throttle Enable Port 2 This bit enables broadcast input rate throttling on Port 2.
Page 392: Switch Engine Admit Non Member Register (Swe_Admt_N_Member)
When set, a received packet is accepted even if the ingress port is not a member of the destination VLAN. The VLAN still must be active in the switch. There is one bit per ingress port. Bits 2,1,0 correspond to switch ports 2,1,0 respectively. Revision 1.4 (08-19-08)
Page 393: Switch Engine Ingress Rate Configuration Register (Swe_Ingrss_Rate_Cfg)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.25 Switch Engine Ingress Rate Configuration Register (SWE_INGRSS_RATE_CFG) Register #: This register, along with the settings accessible via the (SWE_INGRSS_RATE_CMD), is used to configure the ingress rate metering/coloring.
Page 394: Switch Engine Ingress Rate Command Register (Swe_Ingrss_Rate_Cmd)
23. Note: Values outside of the valid range may cause unexpected results. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 184Bh Size: 32 bits Switch Engine Ingress Rate Command Status indicates when the command is finished.
Page 395: 26.1Ingress Rate Table Registers
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.26.1 INGRESS RATE TABLE REGISTERS The ingress rate metering/color table consists of 24 Committed Information Rate (CIR) registers (one per port/priority), a Committed Burst Size register, and an Excess Burst Size register. All metering/color...
Page 396: Switch Engine Ingress Rate Command Status Register (Swe_Ingrss_Rate_Cmd_Sts)
When set, indicates that the read or write command is taking place. This bit is cleared once the command has finished. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 184Ch Size: 32 bits...
Page 397: Switch Engine Ingress Rate Write Data Register (Swe_Ingrss_Rate_Wr_Data)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.28 Switch Engine Ingress Rate Write Data Register (SWE_INGRSS_RATE_WR_DATA) Register #: This register is used to write the ingress rate table registers. BITS 31:16 RESERVED 15:0...
Page 398: Switch Engine Ingress Rate Read Data Register (Swe_Ingrss_Rate_Rd_Data)
This is the read data from the ingress rate table registers as specified in the Switch Engine Ingress Rate Command Register (SWE_INGRSS_RATE_CMD). Refer to Table Registers," on page 395 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 184Eh Size: 32 bits DESCRIPTION Section 14.5.3.26.1, "Ingress Rate...
Page 399: Switch Engine Port 0 Ingress Filtered Count Register (Swe_Filtered_Cnt_Mii)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.30 Switch Engine Port 0 Ingress Filtered Count Register (SWE_FILTERED_CNT_MII) Register #: This register counts the number of packets filtered at ingress on Port 0(Host MAC). This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Page 400: Switch Engine Port 1 Ingress Filtered Count Register (Swe_Filtered_Cnt_1)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1851h Size: 32 bits...
Page 401: Switch Engine Port 2 Ingress Filtered Count Register (Swe_Filtered_Cnt_2)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.32 Switch Engine Port 2 Ingress Filtered Count Register (SWE_FILTERED_CNT_2) Register #: This register counts the number of packets filtered at ingress on Port 2. This count includes packets filtered due to broadcast throttling but does not include packets dropped due to ingress rate limiting (which are counted separately).
Page 402: Switch Engine Port 0 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_Mii)
These bits specify the regenerated priority for received priority 1. Regen0 These bits specify the regenerated priority for received priority 0. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1855h Size: 32 bits...
Page 403: Switch Engine Port 1 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_1)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.34 Switch Engine Port 1 Ingress VLAN Priority Regeneration Table Register (SWE_INGRSS_REGEN_TBL_1) Register #: This register provides the ability to map the received VLAN priority to a regenerated priority. The regenerated priority is used in determining the output priority queue.
Page 404: Switch Engine Port 2 Ingress Vlan Priority Regeneration Table Register (Swe_Ingrss_Regen_Tbl_2)
These bits specify the regenerated priority for received priority 1. Regen0 These bits specify the regenerated priority for received priority 0. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1857h Size: 32 bits...
Page 405: Switch Engine Port 0 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_Mii)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.36 Switch Engine Port 0 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_MII) Register #: This register counts the number of MAC addresses on Port 0(Host MAC) that were not learned or were overwritten by a different address due to address table space limitations.
Page 406: Switch Engine Port 1 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_1)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1859h Size: 32 bits...
Page 407: Switch Engine Port 2 Learn Discard Count Register (Swe_Lrn_Discrd_Cnt_2)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.3.38 Switch Engine Port 2 Learn Discard Count Register (SWE_LRN_DISCRD_CNT_2) Register #: This register counts the number of MAC addresses on Port 2 that were not learned or were overwritten by a different address due to address table space limitations.
Page 408: Switch Engine Interrupt Mask Register (Swe_Imr)
14.5.3.39 Switch Engine Interrupt Mask Register (SWE_IMR) Register #: This register contains the Switch Engine interrupt mask, which masks the interrupts in the Engine Interrupt Pending Register Interrupt Mask bit. Clearing this bit will unmask the interrupts. Refer to on page 49 for more information.
Page 409: Switch Engine Interrupt Pending Register (Swe_Ipr)
14.5.3.40 Switch Engine Interrupt Pending Register (SWE_IPR) Register #: This register contains the Switch Engine interrupt status. The status is double buffered. All interrupts in this register may be masked via the Refer to Chapter 5, "System Interrupts," on page 49...
Page 410 Set A Valid When set, bits 7:2 are valid. Interrupt Pending When set, a packet dropped event(s) is indicated. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION DATASHEET Datasheet TYPE DEFAULT...
Page 411: Buffer Manager Csrs
Buffer Manager CSRs This section details the Buffer Manager (BM) registers. These registers allow configuration and monitoring of the switch buffer levels and usage. A list of the general switch CSRs and their corresponding register numbers is included in 14.5.4.1...
Page 412: Buffer Manager Drop Level Register (Bm_Drop_Lvl)
Each buffer is 128 bytes. Note: A port is “active” when 36 buffers are in use for that port. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C01h Size: 32 bits DESCRIPTION...
Page 413: Buffer Manager Flow Control Pause Level Register (Bm_Fc_Pause_Lvl)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.3 Buffer Manager Flow Control Pause Level Register (BM_FC_PAUSE_LVL) Register #: This register configures the buffer usage level when a Pause frame or backpressure is sent.
Page 414: Buffer Manager Flow Control Resume Level Register (Bm_Fc_Resume_Lvl)
Each buffer is 128 bytes. Note: A port is “active” when 36 buffers are in use for that port. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C03h Size: 32 bits DESCRIPTION...
Page 415: Buffer Manager Broadcast Buffer Level Register (Bm_Bcst_Lvl)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.5 Buffer Manager Broadcast Buffer Level Register (BM_BCST_LVL) Register #: This register configures the buffer usage limits for broadcasts, multicasts, and unknown unicasts. BITS 31:8 RESERVED...
Page 416: Buffer Manager Port 0 Drop Count Register (Bm_Drp_Cnt_Src_Mii)
Note: The counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C05h Size: 32 bits...
Page 417: Buffer Manager Port 1 Drop Count Register (Bm_Drp_Cnt_Src_1)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.7 Buffer Manager Port 1 Drop Count Register (BM_DRP_CNT_SRC_1) Register #: This register counts the number of packets dropped by the Buffer Manager that were received on Port 1.
Page 418: Buffer Manager Port 2 Drop Count Register (Bm_Drp_Cnt_Src_2)
Note: The counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C07h Size: 32 bits...
Page 419: Buffer Manager Reset Status Register (Bm_Rst_Sts)
The initialization is performed upon any reset that resets the switch fabric. Note 14.63 The default value of this bit is 0 immediately following any switch fabric reset and then self- sets to 1 once the ALR table is initialized.
Page 420: Buffer Manager Random Discard Table Command Register (Bm_Rndm_Dscrd_Tbl_Cmd)
1100 1101 1110 1111 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C09h Size: 32 bits Buffer Manager Random Discard Table Read Data Register can be read following a write to this register.
Page 421: Buffer Manager Random Discard Table Write Data Register (Bm_Rndm_Dscrd_Tbl_Wdata)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.11 Buffer Manager Random Discard Table Write Data Register (BM_RNDM_DSCRD_TBL_WDATA) Register #: This register is used to write the Random Discard Weight table. Note: The Random Discard Weight table is not initialized upon reset or power-up. If a random discard is enabled, the full table should be initialized by the host.
Page 422: Buffer Manager Random Discard Table Read Data Register (Bm_Rndm_Dscrd_Tbl_Rdata)
14.5.4.10, "Buffer Manager Random Discard Table Command Register (BM_RNDM_DSCRD_TBL_CMD)". Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C0Bh Size: 32 bits...
Page 423: Buffer Manager Egress Port Type Register (Bm_Egrss_Port_Type)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.13 Buffer Manager Egress Port Type Register (BM_EGRSS_PORT_TYPE) Register #: This register is used to configure the egress VLAN tagging rules. See Removing, and Changing VLAN Tags," on page 79...
Page 424 Identical to Change Tag Port 2 definition above. Egress Port Type Port 0(Host MAC) Identical to Egress Port Type Port 2 definition above. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface DESCRIPTION EGRESS PORT TYPE Section 6.5.6, for additional Section 6.5.6,...
Page 425: Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_00_01)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.14 Buffer Manager Port 0 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_00_01) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED...
Page 426: Buffer Manager Port 0 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_02_03)
These bits specify the egress data rate for the Port 0(Host MAC) priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C0Eh Size: 32 bits...
Page 427: Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_10_11)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.16 Buffer Manager Port 1 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_10_11) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED...
Page 428: Buffer Manager Port 1 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_12_13)
These bits specify the egress data rate for the Port 1 priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C10h Size:...
Page 429: Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (Bm_Egrss_Rate_20_21)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.18 Buffer Manager Port 2 Egress Rate Priority Queue 0/1 Register (BM_EGRSS_RATE_20_21) Register #: This register, along with the the egress rate pacing. BITS 31:26 RESERVED...
Page 430: Buffer Manager Port 2 Egress Rate Priority Queue 2/3 Register (Bm_Egrss_Rate_22_23)
These bits specify the egress data rate for the Port 2 priority queue 2. The rate is specified in time per byte. The time is this value plus 1 times 20nS. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C12h Size:...
Page 431: Buffer Manager Port 0 Default Vlan Id And Priority Register (Bm_Vlan_Mii)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.20 Buffer Manager Port 0 Default VLAN ID and Priority Register (BM_VLAN_MII) Register #: This register is used to specify the default VLAN ID and priority of Port 0(Host MAC).
Page 432: Buffer Manager Port 1 Default Vlan Id And Priority Register (Bm_Vlan_1)
Default VLAN ID These bits specify the default that is used when a tag is inserted or changed on egress. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C14h Size: 32 bits...
Page 433: Buffer Manager Port 2 Default Vlan Id And Priority Register (Bm_Vlan_2)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.22 Buffer Manager Port 2 Default VLAN ID and Priority Register (BM_VLAN_2) Register #: This register is used to specify the default VLAN ID and priority of Port 2.
Page 434: Buffer Manager Port 0 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_Mii)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C16h Size: 32 bits...
Page 435: Buffer Manager Port 1 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_1)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.24 Buffer Manager Port 1 Ingress Rate Drop Count Register (BM_RATE_DRP_CNT_SRC_1) Register #: This register counts the number of packets received on Port 1 that were dropped by the Buffer Manager due to ingress rate limit discarding (Red and random Yellow dropping).
Page 436: Buffer Manager Port 2 Ingress Rate Drop Count Register (Bm_Rate_Drp_Cnt_Src_2)
Note: This counter will stop at its maximum value of FFFF_FFFFh. Minimum rollover time at 100Mbps is approximately 481 hours. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C18h Size: 32 bits...
Page 437: Buffer Manager Interrupt Mask Register (Bm_Imr)
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 14.5.4.26 Buffer Manager Interrupt Mask Register (BM_IMR) Register #: This register contains the Buffer Manager interrupt mask, which masks the interrupts in the Manager Interrupt Pending Register the Interrupt Mask bit.
Page 438: Buffer Manager Interrupt Pending Register (Bm_Ipr)
10 = Port 2 11 = RESERVED Status B Pending When set, bits 13:8 are valid. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1C21h Size: 32 bits Buffer Manager Interrupt Mask Register (BM_IMR) for more information.
Page 439 High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet BITS Drop Reason A When bit 0 is set, these bits indicate the reason a packet was dropped. See the Drop Reason B description above for definitions of each value of this field.
Page 440: Chapter 15 Operational Characteristics
Supply Voltage (VDD33A1, VDD33A2, VDD33BIAS, VDD33IO)....+3.3V +/- 300mV Ambient Operating Temperature in Still Air (T **Proper operation of the LAN9312 is guaranteed only within the ranges specified in this section. Revision 1.4 (08-19-08)
Page 441: Power Consumption
15.3 Power Consumption This section details the power consumption of the LAN9312. Power consumption values are provided for both the device-only, and for the device plus the Ethernet components on ports 1 and 2. Table 15.1 Supply and Current (10BASE-T Full-Duplex) PARAMETER Supply current at 3.3V...
Page 442: Dc Specifications
Signal Amplitude Symmetry Signal Rise and Fall Time Rise and Fall Symmetry Duty Cycle Distortion Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 15.3 I/O Buffer Characteristics -0.3 1.01 1.18 1.35 1.39...
Page 443: Ac Specifications
Note 15.10 Min/max voltages guaranteed as measured with 100 Ω resistive load. 15.5 AC Specifications This section details the various AC timing specifications of the LAN9312. Note: The I C timing adheres to the Philips I Specification for detailed I 15.5.1...
Page 444: Reset And Configuration Strap Timing
Note: Device configuration straps are latched as a result of nRST assertion. Refer to "Configuration Straps," on page 40 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Section 4.2, "Resets," on page 36 rstia odad Figure 15.2 nRST Reset Pin Timing...
Page 445: Power-On Configuration Strap Valid Timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.5.3 Power-On Configuration Strap Valid Timing This diagram illustrates the configuration strap valid timing requirements in relation to power-on. In order for valid configuration strap values to be read at power-on, the following timing requirements must be met.
Page 446: Pio Read Cycle Timing
These signals may be asserted and de-asserted in any order. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for a functional description of this mode. cycle csdv Figure 15.4 PIO Read Cycle Timing...
Page 447: Pio Burst Read Cycle Timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.5.5 PIO Burst Read Cycle Timing Please refer to Section 8.4.5, "PIO Burst Reads," on page 107 A[x:5], END_SEL A[4:2] nCS, nRD D[31:0] Figure 15.5 PIO Burst Read Cycle Timing Table 15.9 PIO Burst Read Cycle Timing Values...
Page 448: Rx Data Fifo Direct Pio Read Cycle Timing
Note: A RX Data FIFO direct PIO read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de- asserted in any order. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface cycle csdv DESCRIPTION...
Page 449: Rx Data Fifo Direct Pio Burst Read Cycle Timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.5.7 RX Data FIFO Direct PIO Burst Read Cycle Timing Please refer to Section 8.4.7, "RX Data FIFO Direct PIO Burst Reads," on page 109 description of this mode.
Page 450: Pio Write Cycle Timing
These signals may be asserted and de-asserted in any order. Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for a functional description of this mode. cycle Figure 15.8 PIO Write Cycle Timing...
Page 451: Tx Data Fifo Direct Pio Write Cycle Timing
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 15.5.9 TX Data FIFO Direct PIO Write Cycle Timing Please refer to Section 8.4.9, "TX Data FIFO Direct PIO Writes," on page 111 description of this mode.
Page 452: Microwire Timing
EEDI valid after EECS high (VERIFY) cshdv EEDI hold after EECS low (VERIFY) dhcsl EECS low Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface for a functional description of this serial interface. ckcyc dvckh ckhdis dsckh...
Page 453: Clock Circuit
15.6 Clock Circuit The LAN9312 can accept either a 25MHz crystal (preferred) or a 25MHz single-ended clock oscillator (+/- 50ppm) input. If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with a nominal 0-3.3V clock signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
Page 454: Chapter 16 Package Outlines
14.00 0.45 0.60 0.13 0.18 0.09 0.40 BSC 0.00 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface 1.20 Overall Package Height 0.15 1.05 Body Thickness 16.20 14.20 X/Y Plastic Body Size 0.75 Lead Foot Length 0.23...
Page 455: Figure 16.2 Lan9312 128-Vtqfp Recommended Pcb Land Pattern
3. Dimensions D1 and E1 do not include mold protrusions. Maximum allowed protrusion is 0.25mm per side. D1 and E1 are maximum plastic body size dimensions including mold mismatch. 4. The pin 1 identifier may vary, but is always located within the zone indicated Figure 16.2 LAN9312 128-VTQFP Recommended PCB Land Pattern SMSC LAN9312 DATASHEET...
Page 456: 128-Xvtqfp Package Outline
High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet 16.2 128-XVTQFP Package Outline Figure 16.3 LAN9312 128-XVTQFP Package Definition Revision 1.4 (08-19-08) SMSC LAN9312 DATASHEET...
Page 457: Figure 16.4 Lan9312 128-Xvtqfp Recommended Pcb Land Pattern
4. Dimensions D2 and E2 represent the size of the exposed pad. The exposed pad shall be coplanar with the bottom of the package within 0.05mm. 5. The pin 1 identifier may vary, but is always located within the zone indicated Figure 16.4 LAN9312 128-XVTQFP Recommended PCB Land Pattern SMSC LAN9312 REMARKS 1.20...
Page 458: Chapter 17 Revision History
Section 15.6, "Clock Circuit," on page 453 Revision 1.4 (08-19-08) High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Table 17.1 Customer Revision History Added note at end of WUFF section and to the BCAST bit of the MAC_CR register stating:...

SMSC LAN9312 Datasheet

Chapter 1 Preface

Chapter 2 Introduction

Chapter 3 Pin Description and Configuration

Chapter 4 Clocking, Resets, and Power Management

Chapter 5 System Interrupts

Chapter 6 Switch Fabric

Chapter 7 Ethernet Phys

Chapter 8 Host Bus Interface (HBI)

Chapter 9 Host MAC

Chapter 10 Serial Management

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Summary of Contents for SMSC LAN9312