S3 Incorporated Trio64V+ Manuals

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S3 Incorporated Trio64V+ Manual

S3 Incorporated Trio64V+ Manual (320 pages)

Integrated Graphics/Video Accelerator

Brand: S3 Incorporated | Category: Computer Hardware | Size: 15.89 MB

Table of Contents

Table of Contents
4
List of Figures
7
List of Tables
9
Section 1: Introduction
10
- Overview
  11
- S3 Streams Processor
  11
- S3 Scenic Highway
  12
- Trio64V+ CHANGES from the Trio64
  12
Section 2: Mechanical Data
14
- Thermal Specifications
  14
- Mechanical Dimensions
  14
Section 3: Pins
16
- Pinout Diagrams
  16
- Trio64V+ PCI Bus Pinout
  17
- LPB Mode
  17
- Trio64V+ VL-Bus Pinout
  18
- Pin Descriptions
  19
- Pin Descriptions - LPB Mode
  19
- Cycle
  20
- Host Interface
  26
- Pin Lists
  27
- Numerical Pin Listing
  30
Section 4: Electrical Data
36
- Maximum Ratings
  36
- DC Specifications
  36
- Absolute Maximum Ratings
  36
- Ramdac/Clock Synthesizer DC Specifications
  36
- RAMDAC Characteristics
  36
- Digital DC Specifications
  37
- Ac Specifications
  38
  - RAMDAC AC Specifications
    38
  - Clock Timing
    39
  - Clock Waveform Timing
    39
  - Input/Output Timing
    40
  - Input Timing
    40
  - SCLK-Referenced Input Timing
    40
  - LCLK-Referenced Input Timing
    41
  - MCLK-Referenced Input Timing
    41
  - Output Timing
    42
  - SCLK-Referenced Output Timing
    42
  - LCLK-Referenced Output Timing
    43
  - MCLK-Referenced Output Timing
    43
  - Feature Connector Timing - Output
    43
  - Connector
    44
  - Feature Connector Timing
    44
Section 5: Reset and Initialization
46
- Definition of PD
  47
Section 6: System Bus Interfaces
50
- Pci Bus Interface
  50
  - Pciconfiguration
    50
  - PCI Bus Cycles
    50
  - Basic PCI Read Cycle
    51
  - Basic PCI Write Cycle
    51
  - PCI Disconnect Example a
    52
  - PCI Disconnect Example B
    52
  - PCI Configuration Write Cycle
    53
  - PCI Configuration Read Cycle
    53
- Vl-Bus Interface
  55
  - VL-Bus Cycles
    55
  - VL-Bus Upper Address Decoding
    55
  - VL-Bus Read Cycle
    56
  - Wait-State VL-Bus Write Cycle
    57
Section 7: Display Memory
58
Section 8: RAMDAC Functionality
70
- Operating Modes
  70
- Internal RAMDAC Block Diagram
  70
- Color Modes
  71
  - Bits/Pixel - Mode 0
    71
  - Output-Doubled 8 Bits/Pixel
    71
  - 15/16-Bits/Pixel - Modes 9 and 10
    72
  - Packed 24 Bits/Pixel - Mode
    72
  - Bits/Pixel - Mode 13
    72
- Ramdac Register Access
  72
- Ramdac Snooping
  72
- Sense Generation
  72
- Power Control
  72
- Registers
  72
Section 9: Clock Synthesis and Control
74
- Clock Synthesis
  74
- PLL R Parameter Decoding
  74
- Clock Reprogramming
  75
- Dclk Control
  76
Section 10: Streams Processor
78
- Input Streams
  78
  - Primary Stream Input
    79
  - Secondary Stream Input
    79
  - Hardware Cursor Generation
    79
  - Frame Buffer Organization/Double Buffering
    79
  - Register Fields Used for Specifying Frame Buffer Organization and Double Buffering
    80
  - Screen Definition Parameters
    82
  - Register Fields Used for Scaling up the Secondary Stream
    83
  - Hardware Interface
    87
  - Scenic/Mx2 Write
    88
  - Scenic/Mx2 Read
    88
  - Scenic/Mx2 Compressed Transfer (Ready)
    89
  - Scenic/Mx2 Stopping a
    90
  - Scenic/Mx2 Video Input (Trio64V+ Ready)
    91
  - Scenic/Mx2 Video Input (Trio64V+ Not Ready)
    91
  - Video 81N or 16 Mode Input
    93
  - LPB-Enabled Pin Assignments
    96
  - BIOS ROM VL-Bus Configuration Interface
    99
  - BIOS ROM Read Functional
    100
  - General Input Port Interface (VL-Bus)
    101
  - General Input Port Timing
    102
  - General Output Port Interface (VL-Bus)
    103
  - General Output Port Timing (VL-Bus)
    103
  - Connector Configuration
    104
  - Tri064V
    108
  - VGA Register Access Control Extensions
    112
  - Standard VGA Registers Modified
    114
  - Enhanced Registers Memory Mapping
    120
  - New MMIO Addresses
    121
  - VGA Registers
    285
  - S3 VGA Registers
    296
  - System Control Registers
    296
  - System Extension Registers
    298
  - Enhanced Commands Registers
    302
  - Streams Processor Registers
    306
  - LPB Registers
    310
  - PCI Configuration Space
    313

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