General Input Port Timing - S3 Incorporated Trio64V+ Manual

Trio64V+ Integrated Graphics/Video Accelerator
S3 Incorporated
T1
T2
T3
T4
T5
T6 T7
5CLK
GPI05TR \ /
'--. _ _ _ _ _ _ - J
50[7:0]
~~
_ _ _ _ _ _ _ _ _ _ _ _ _
---,'fItI&
VGIPVL
Figure 12-5. General Input Port Timing (VL-Bus)
3. The data is read from an external buffer by
a read of port 3C8H (the same as the DAC
Write Index off-chip register).
When GPIOSTR is asserted, the data is immedi-
ately placed on SD[7:0]. The functional timing for
this operation is shown in Figure 12-5. The entire
cycle from assertion of SADS to data being avail-
able on SD[7:0] takes approximately 18-20
SCLKs.
T1
DCLK
12.4 GENERAL OUTPUT PORT
The Tri064V+ provides a 4-bit General Output
Port (GOP) for PCI configurations as part of its
LPB function. To implement this:
1. Disable all other LPB uses.
2. Programmed the desired output in
MMFF1C_ 4-0.
4. Program SR1C_1-0 to 01 b to enable output
of STWR on pin 190.
5. Write (anything) to CR5C. The data in
MMFF1C_3-0 are immediately driven onto
T2
T3
STWR , ' - -_ _ _ _ _ _
..,F
LATCH
LD[3:0]
-m
' f llt.
..... - - - - - - - - - . . . . VLPBGOP
Figure 12-6. General 1/0 Port Timing (PCI)
MISCELLANEOUS FUNCTIONS 12-5