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S3 Incorporated Manuals
Computer Hardware
Trio64V+
Manual
S3 Incorporated Trio64V+ Manual
Integrated graphics/video accelerator
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
List of Figures
List of Tables
Section 1: Introduction
Overview
S3 Streams Processor
S3 Scenic Highway
Trio64V+ CHANGES from the Trio64
Section 2: Mechanical Data
Thermal Specifications
Mechanical Dimensions
Section 3: Pins
Pinout Diagrams
Trio64V+ PCI Bus Pinout
LPB Mode
Trio64V+ VL-Bus Pinout
Pin Descriptions
Pin Descriptions - LPB Mode
Cycle
Host Interface
Pin Lists
Numerical Pin Listing
Section 4: Electrical Data
Maximum Ratings
DC Specifications
Absolute Maximum Ratings
Ramdac/Clock Synthesizer DC Specifications
RAMDAC Characteristics
Digital DC Specifications
Ac Specifications
RAMDAC AC Specifications
Clock Timing
Clock Waveform Timing
Input/Output Timing
Input Timing
SCLK-Referenced Input Timing
LCLK-Referenced Input Timing
MCLK-Referenced Input Timing
Output Timing
SCLK-Referenced Output Timing
LCLK-Referenced Output Timing
MCLK-Referenced Output Timing
Feature Connector Timing - Output
Connector
Feature Connector Timing
Section 5: Reset and Initialization
Definition of PD
Section 6: System Bus Interfaces
Pci Bus Interface
Pciconfiguration
PCI Bus Cycles
Basic PCI Read Cycle
Basic PCI Write Cycle
PCI Disconnect Example a
PCI Disconnect Example B
PCI Configuration Write Cycle
PCI Configuration Read Cycle
Vl-Bus Interface
VL-Bus Cycles
VL-Bus Upper Address Decoding
VL-Bus Read Cycle
Wait-State VL-Bus Write Cycle
Section 7: Display Memory
Display Memory Configurations
Memory Size/Chip Count Configurations
Display Memory Refresh
Display Memory Functional Timing
Fast Page Mode Read Cycle
Fast Page Mode Write Cycle
Fast Page Mode Read/Modify/Write Cycle
EDO Mode Read Cycle
EDO Mode Read/Modify/Write Cycle
1-Cycle Edo Dram Support
Display Memory Access Control
Section 8: RAMDAC Functionality
Operating Modes
Internal RAMDAC Block Diagram
Color Modes
Bits/Pixel - Mode 0
Output-Doubled 8 Bits/Pixel
15/16-Bits/Pixel - Modes 9 and 10
Packed 24 Bits/Pixel - Mode
Bits/Pixel - Mode 13
Ramdac Register Access
Ramdac Snooping
Sense Generation
Power Control
Registers
Section 9: Clock Synthesis and Control
Clock Synthesis
PLL R Parameter Decoding
Clock Reprogramming
Dclk Control
Section 10: Streams Processor
Input Streams
Primary Stream Input
Secondary Stream Input
Hardware Cursor Generation
Frame Buffer Organization/Double Buffering
Register Fields Used for Specifying Frame Buffer Organization and Double Buffering
Screen Definition Parameters
Register Fields Used for Scaling up the Secondary Stream
Hardware Interface
Scenic/Mx2 Write
Scenic/Mx2 Read
Scenic/Mx2 Compressed Transfer (Ready)
Scenic/Mx2 Stopping a
Scenic/Mx2 Video Input (Trio64V+ Ready)
Scenic/Mx2 Video Input (Trio64V+ Not Ready)
Video 81N or 16 Mode Input
LPB-Enabled Pin Assignments
BIOS ROM VL-Bus Configuration Interface
BIOS ROM Read Functional
General Input Port Interface (VL-Bus)
General Input Port Timing
General Output Port Interface (VL-Bus)
General Output Port Timing (VL-Bus)
Connector Configuration
Tri064V
VGA Register Access Control Extensions
Standard VGA Registers Modified
Enhanced Registers Memory Mapping
New MMIO Addresses
VGA Registers
S3 VGA Registers
System Control Registers
System Extension Registers
Enhanced Commands Registers
Streams Processor Registers
LPB Registers
PCI Configuration Space
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Table of Contents
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Section 1: Introduction
3
Overview
4
Pinout Diagrams
5
Section 3: Pins
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