User Manuals: rtd DM35418HR PCIe/104 Analog-to-Digital

Manuals and User Guides for rtd DM35418HR PCIe/104 Analog-to-Digital. We have 1 rtd DM35418HR PCIe/104 Analog-to-Digital manual available for free PDF download: User Manual

rtd DM35418HR User Manual (56 pages)

PCI Express Data Acquisition Board

Brand: rtd | Category: PCI Card | Size: 2 MB

Table of Contents
4
Introduction
8
Product Overview
8
Board Features
8
Ordering Information
8
Table 1: Ordering Options
8
Contact Information
9
Sales Support
9
Technical Support
9
Specifications
10
Operating Conditions
10
Electrical Characteristics
10
Table 2: Operating Conditions
10
Table 3: Electrical Characteristics
10
Functional Characteristics
11
Table 4: Functional Characteristics
11
Analog Input Histograms
12
Figure 1: Channel FFT
12
Figure 2: Histogram
12
Board Connection
13
Board Handling Precautions
13
Physical Characteristics
13
Figure 3: Board Dimensions
13
Connectors and Jumpers
14
Cn1(Top) & CN2(Bottom): Pcie Connector
14
Figure 4: Board Connections
14
External I/O Connectors
15
CN3: Digital I/O Connector
15
Table 5: CN3 Single-Ended Mode Pin-Out
15
CN4: Analog I/O Connector
16
CN5: Syncbus Connector
16
Other Connectors
16
Jumpers
16
Table 6: CN4 Differential Mode Pin-Out
16
Table 7: CN4 Single-Ended Mode Pin-Out
16
Table 8: CN5 Pin-Out
16
Leds
17
LED 0: Clock Reset
17
LED 1: Clock Status
17
LED 2: SYNCBUS Lock
17
LED 3: Clock Select
17
Steps for Installing
18
Figure 5: Example 104™Stack
18
IDAN Connections
19
Module Handling Precautions
19
Physical Characteristics
19
Figure 6: IDAN Dimensions
19
DM35418 External I/O Connectors
20
Analog I/O and Syncbus Connector - 68-Pin Subminiature "D" Female Connector
20
Table 9: IDAN- DM35418 68-Pin Subminiature "D" Connector
20
Analog I/O and Syncbus Connector - 62-Pin High Density "D" Female Connector
21
Table 10: IDAN- DM35418 62-Pin High Density "D" Connector
21
Digital I/O Connector - 37-Pin High Density "D" Female Connector
22
Table 11: IDAN- DM35418 37-Pin High Density "D" Connector
22
DM35218 External I/O Connectors
23
Analog I/O and Syncbus Connector - 68-Pin Subminiature "D" Female Connector
23
Table 12: IDAN- DM35218 68-Pin Subminiature "D" Connector
23
Analog I/O and Syncbus Connector - 62-Pin High Density "D" Female Connector
24
Table 13: IDAN- DM35218 62-Pin High Density "D" Connector
24
Digital I/O Connector - 37-Pin High Density "D" Female Connector
25
Table 14: IDAN- DM35218 37-Pin High Density "D" Connector
25
Bus Connectors
26
Cn1(Top) & CN2(Bottom): Pcie Connector
26
Steps for Installing
26
Figure 7: Example IDAN System
26
Functional Description
27
Block Diagram
27
FPGA with DMA Engine
27
Syncbus
27
Figure 8: DM35418HR/DM35218HR Block Diagram
27
Digital I/O
28
Temperature Sensor
28
Analog Input
28
Single-Ended Input Mode
28
Differential Input Mode
28
Full-Scale Input Range
28
Bipolar/Unipolar Mode
28
Initializing the ADC Converter
29
Simplified Block Diagram of Analog Input
29
Figure 9: Analog Input Front End
29
Table 15: ADC Full-Scale Settings
29
Input Connection Examples
30
5.4.3.1. Single Ended, Bipolar, ±10V Full-Scale Range
30
5.4.3.2. Differential, Bipolar, ±10V Full-Scale Range
30
Figure 10: Bipolar Single-Ended Example
30
Figure 11: Bipolar Differential Example
30
5.4.3.3. Single Ended, Unipolar, 0-10V Full-Scale Range
31
5.4.3.4. Differential, Unipolar, 0-10V Full-Scale Range
31
Figure 12: Unipolar Single Ended Example
31
Figure 13: Unipolar Differential Example
31
5.4.3.5. ADC Gain and Offset Test
32
Analog Output
32
Initializing the DAC Converter
32
Figure 14: Bipolar Offset and Gain Test Circuit
32
Simplified Block Diagram of Analog Output
33
Figure 15: Analog Output
33
Table 16: DAC Full-Scale Settings
33
Table 17: Key DAC Bit Weight
33
Register Address Space
34
Register Types
34
Function Block Mapping
34
Table 18: Function Block Mapping
34
BAR0: General Board Control
35
GBC_FMT (Read-Only)
35
GBC_REV (Read-Only)
35
GBC_BRD_RST (Read/Write)
35
GBC_PDP (Read-Only)
35
GBC_BUILD (Read-Only)
35
GBC_SYS_CLK_FREQ (Read Only)
35
Table 19: Base Functional Block
35
GBC_USER_ID (Read Only)
36
GBC_IRQ_STATUS (Read/Clear)
36
GBC_DIRQ_STATUS (Read/Clear)
36
GBC_EOI (Read/Clear)
36
Fbn_Id (Read-Only)
36
Fbn_Offset (Read-Only)
36
Fbn_Offset_Dma (Read-Only)
36
BAR2: Functional Block Standard DMA
37
Fb_Dmam_Last_Action (Read/Write)
37
Fb_Dmam_Setup (Read/Write)
37
Table 20: DMA Registers
37
Fb_Dmam_Stat_Used (Read/Write)
38
Fb_Dmam_Stat_Invalid (Read/Write)
38
Fb_Dmam_Stat_Overflow (Read/Write)
38
Fb_Dmam_Stat_Underflow (Read/Write)
38
Fb_Dmam_Stat_Complete (Read/Write)
38
Fb_Dmam_Current_Buffer (Read-Only)
38
Fb_Dmam_Count (Read-Only)
38
Fb_Dmam_Rd_Fifo_Cnt(Read-Only)
38
Fb_Dmam_Wr_Fifo_Cnt(Read-Only)
38
Fb_Dmam_Addressn (Read/Write)
38
Fb_Dmam_Ctrln (Read/Write)
39
Fb_Dmam_Statn (Read/Clear)
39
BAR2: Functional Block Header Registers
39
FB_ID (Read-Only)
39
FB_DMA_CHANNELS (Read -Only)
39
FB_DMA_BUFFERS (Read-Only)
39
Table 21: Functional Block Header
39
BAR2: Analog to Digital Converter (ADC)
40
Mode_Status (Read/Write, Read-Only)
40
Table 22: Multi-Channel A/D Functional Block
40
CLK_SRC (Read/Write)
41
START_TRIG (Read/Write)
41
STOP_TRIG (Read/Write)
41
CLK_DIV (Read/Write)
41
CLK_DIV_CNTR (Read Only)
41
PRE_TRIGGER_CAPTURE (Read/Write)
42
POST_STOP_CAPTURE (Read/Write)
42
SAMPLE_CNT (Read Only)
42
INT_ENA (Maskable Read/Write)
42
INT_STAT (Read/Clear)
42
Clk_Src_Gbln
42
AD_CONFIG (Maskable Read/Write)
42
FRONT_END_CONFIG (Maskable Read/Write)
43
Chn_Fifo_Data_Cnt (Read)
43
FILTER (Read/Write)
43
Figure 16: Filter Response with each ORDER Value
43
Int_Stat(Read/Clear)
44
INT_ENA (Read/Write)
44
THRESH_LOW (Read/Write)
44
THRESH_HIGH (Read/Write)
44
LAST_SAMPLE (Read-Only)
44
BAR2: Digital to Analog Converter (DAC)
45
Mode_Status (Read/Write, Read-Only)
45
Table 23: Multi-Channel DAC Functional Block
45
CLK_SRC (Read/Write)
46
START_TRIG (Read/Write)
46
STOP_TRIG (Read/Write)
46
CLK_DIV (Read/Write)
46
CLK_DIV_CNTR (Read Only)
46
POST_STOP_CONVERSIONS (Read/Write)
47
CONVERSION_CNT (Read Only)
47
INT_ENA (Maskable Read/Write)
47
INT_STAT (Read/Clear)
47
Clk_Src_Gbln
47
CONFIG (Maskable Read/Write)
47
FRONT_END_CONFIG (Maskable Read/Write)
47
Table 24: DAC Full-Scale Settings
47
Chn_Fifo_Data_Cnt (Read)
48
INT_STAT (Read/Clear)
48
INT_ENA (Read/Write)
48
LAST_CONVERSION (Read/Write)
48
BAR2: Digital I/O (DIO)
49
Function Block Register Map
49
DIO_INPUT_VAL (Read Only)
49
DIO_OUTPUT_VAL (Read/Write)
49
DIO_DIRECTION (Read/Write)
49
Table 25: Digital I/O Functional Block
49
BAR2: Temperature Sensor
50
Function Block Register Map
50
TEMPERATURE_VAL (Read Only)
50
Table 26: Temperature Sensor Functional Block
50
BAR2: Syncbus Driver
51
CLK_SEL (Read/Clear)
51
PLL_LOCKED (Read Only)
51
TERM_ENABLE (Read/Write)
51
Table 27: Syncbus Functional Block
51
SB_ N_Clk_Src (Read/Write)
52
DIRECTION (Read/Write)
52
Clk_Src_Gbln
52
Troubleshooting
53
Additional Information
54
PC/104 Specifications
54
PCI and PCI Express Specification
54
Limited Warranty
55

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User Manuals: rtd DM35418HR PCIe/104 Analog-to-Digital

rtd DM35418HR User Manual (56 pages)

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