rtd DM35425 Manuals

Manuals and User Guides for rtd DM35425. We have 1 rtd DM35425 manual available for free PDF download: User Manual

rtd DM35425 User Manual

rtd DM35425 User Manual (60 pages)

PCI Express Data Acquisition Board

Brand: rtd | Category: I/O Systems | Size: 2 MB

Table of Contents

Table of Contents
3
1 Introduction

8
- Product Overview
  8
- Board Features
  8
- Ordering Information
  8
- Contact Information
  8
  - Sales Support
    8
  - Table 1: Ordering Options
    8
  - Technical Support
    9
2 Specifications

10
- Operating Conditions
  10
- Electrical Characteristics
  10
  - Table 2: Operating Conditions
    10
  - Table 3: Electrical Characteristics
    10
  - Analog Input FFT Plots
    12
  - Analog Input Histograms
    12
  - Figure 1: Channel FFT
    12
  - Figure 2: Histogram
    12
3 Board Connection

13
4 IDAN Connections

18
5 Functional Description

24
- Block Diagram
  24
- Control Interface with DMA Engine
  24
- Analog Input
  24
- Figure 8: DM35425 Block Diagram
  24
- Analog Input
  25
  - Simplified Block Diagram of Analog Input
    25
    
    Single-Ended Input Mode
    25
    
    Differential Input Mode
    25
    
    Full-Scale Input Range
    25
    
    Bipolar/Unipolar Mode
    26
    
    Channel Delay
    26
    
    Effective Sampling Rate
    26
    
    Table 12: ADC Bipolar Code ( ±5 V Input Range)
    26
    
    Table 13: ADC Bipolar Code ( ±10 V Input Range)
    26
    
    Table 14: ADC Unipolar Code ( 0 to 10 V Input Range)
    26
- Analog Output
  27
  - Simplified Block Diagram of Analog Output
    27
- Advanced Digital I/O
  28
  - Dma
    28
  - Advanced Interrupts
    28
  - Parallel Bus Mode
    28
- External Clocking
  29
6 Register Address Space

30
- Register Types
  30
- Clock Source
  30
- BAR0 - General Board Control
  31
  - GBC_EOI (Read/Clear)
    31
  - GBC_REV (Read-Only)
    31
  - GBC_FMT (Read-Only)
    31
  - GBC_PDP (Read-Only)
    31
  - GBC_BUILD (Read-Only)
    31
  - Table 15: BAR0 Registers
    31
  - GBC_SYS_CLK_FREQ (Read Only)
    32
  - GBC_IRQ_STATUS (Read/Clear)
    32
  - GBC_DIRQ_STATUS (Read/Clear)
    32
  - Fbn_Id (Read-Only)
    32
  - Fbn_Offset (Read-Only)
    32
  - Fbn_Offset_Dma (Read-Only)
    32
- BAR2 - Functional Block Standard DMA
  33
- BAR2 - ADC Functional Block
  36
  - Table 17: Multi-Channel ADC Functional Block
    36
  - CLK_DIV (Read/Write)
    37
  - CLK_SRC (Read/Write)
    37
  - FB_DMA_BUFFERS (Read-Only)
    37
  - FB_DMA_CHANNELS (Read -Only)
    37
  - Mode_Status (Read/Write, Read-Only)
    37
  - START_TRIG (Read/Write)
    37
  - STOP_TRIG (Read/Write)
    37
  - Clk_Busn
    38
  - CLK_DIV_CNTR (Read Only)
    38
  - INT_ENA (Maskable Read/Write)
    38
  - INT_STAT (Read/Clear)
    38
  - POST_STOP_CAPTURE (Read/Write)
    38
  - PRE_TRIGGER_CAPTURE (Read/Write)
    38
  - SAMPLE_CNT (Read Only)
    38
  - Chn_Fifo_Data_Cnt (Read)
    39
  - Chn_Filter (Read/Write)
    39
  - Chn_Front_End_Config (Maskable Read/Write)
    39
  - Table 18: ADC Full-Scale Settings
    39
  - Chn_Thresh_Ena (Read/Write)
    40
  - Chn_Thresh_Low (Read/Write)
    40
  - Chn_Thresh_Stat(Read/Clear)
    40
  - Figure 9: Filter Response with each ORDER Value
    40
  - Chn_Last_Sample (Read-Only)
    41
  - Chn_Thresh_High (Read/Write)
    41
  - CH_FIFO_ACCESS (Read/Write)
    41
- BAR2 - DAC Functional Block
  42
  - FB_ID (Read-Only)
    42
  - FB_DMA_CHANNELS (Read -Only)
    42
  - FB_DMA_BUFFERS (Read-Only)
    42
  - Mode_Status (Read/Write, Read-Only)
    42
  - Table 19: Multi-Channel DAC Functional Block
    42
  - CLK_SRC (Read/Write)
    43
  - START_TRIG (Read/Write)
    43
  - STOP_TRIG (Read/Write)
    43
  - CLK_DIV (Read/Write)
    43
  - CLK_DIV_CNTR (Read Only)
    43
  - POST_STOP_CONVERSIONS (Read/Write)
    43
  - CONVERSION_CNT (Read Only)
    43
  - INT_ENA (Maskable Read/Write)
    44
  - INT_STAT (Read/Clear)
    44
  - Clk_Busn
    44
  - CH_FRONT_END_CONFIG (Maskable Read/Write)
    44
  - Table 20: DAC Full-Scale Settings
    44
  - Chn_Fifo_Data_Cnt (Read)
    45
  - Ch_Marker_Stat(Read/Clear)
    45
  - CH_MARKER_ENA (Read/Write)
    45
  - CH_LAST_CONVERSION (Read/Write)
    45
  - CH_FIFO_ACCESS (Read/Write)
    45
- BAR2 - Advanced Digital I/O Functional Block
  46
  - FB_ID (Read-Only)
    46
  - FB_DMA_CHANNELS (Read -Only)
    46
  - FB_DMA_BUFFERS (Read-Only)
    46
  - Mode_Status (Read/Write, Read-Only)
    46
  - Table 21: Digital I/O Functional Block
    46
  - CLK_SRC (Read/Write)
    47
  - START_TRIG (Read/Write)
    47
  - STOP_TRIG (Read/Write)
    47
  - CLK_DIV (Read/Write)
    47
  - CLK_DIV_CNTR (Read Only)
    47
  - PRE_TRIGGER_CAPTURE (Read/Write)
    48
  - POST_STOP_CAPTURE (Read/Write)
    48
  - SAMPLE_CNT (Read Only)
    48
  - INT_ENA (Maskable Read/Write)
    48
  - INT_STAT (Read/Clear)
    48
  - Clk_Busn
    48
  - DIO_INPUT (Read Only)
    49
  - DIO_OUTPUT (Read/Write)
    49
  - DIO_DIRECTION (Read/Write)
    49
  - ADV_INT_MODE (Read/Write)
    50
  - ADV_INT_MASK (Read/Write)
    50
  - ADV_INT_COMP (Read/Write)
    50
  - ADV_INT_CAPT (Read/Write)
    50
  - P_BUS_EN (Read/Write)
    50
  - P_BUS_READY_EN (Read/Write)
    50
  - CH_FIFO_ACCESS (Read/Write)
    50
- BAR2 - External Clocking Functional Block
  51
  - FB_ID (Read-Only)
    51
  - FB_DMA_CHANNELS (Read -Only)
    51
  - FB_DMA_BUFFERS (Read-Only)
    51
  - EXT_CLK_IN (Read-Only)
    51
  - EXT_CLK_GATE_IN (Read Only)
    51
  - EXT_CLK_DIR (Read/Write)
    51
  - Table 22:External Clocking Functional Block
    51
  - EXT_CLK_EDGE (Read/Write)
    52
  - Ext_Clk_Pwn (Read/Write)
    52
  - Ext_Clkn_Cfg (Read/Write)
    52
- Required Equipment
  53
- Figure 10: DM35425HR Trimpots
  53
7 Calibration

53
8 Troubleshooting

57
9 Additional Information

58
- PC/104 Specifications
  58
- PCI and PCI Express Specification
  58
10 Limited Warranty

59

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