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Manuals and User Guides for Renesas H8/3693. We have
1
Renesas H8/3693 manual available for free PDF download: Hardware Manual
Renesas H8/3693 Hardware Manual (450 pages)
16-Bit Single-Chip Microcomputer
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2 MB
Table of Contents
Keep Safety First in Your Circuit Designs
3
Notes Regarding These Materials
3
General Precautions on Handling of Product
4
Configuration of this Manual
5
Table of Contents
9
Features
29
I 2 C Bus Interface
29
Section 1 Overview
29
Section 1 Overview
30
Internal Block Diagram
32
Figure 1.1 Internal Block Diagram of H8/3694 Group of F-ZTAT TM and Mask-ROM Versions
32
Figure 1.2 Internal Block Diagram of H8/3694N (EEPROM Stacked Version)
33
Pin Arrangement
34
Figure 1.3 Pin Arrangement of H8/3694 Group of F-ZTAT TM and Mask-ROM Versions (FP-64E, FP-64A)
34
Figure 1.4 Pin Arrangement of H8/3694 Group of F-ZTAT TM and Mask-ROM Versions (FP-48F, FP-48B, TNP-48)
35
Figure 1.5 Pin Arrangement of H8/3694N (EEPROM Stacked Version) (FP-64E)
36
Pin Functions
37
Table 1.1 Pin Functions
37
Section 2 CPU
41
Address Space and Memory Map
42
Figure 2.1 Memory Map (1)
42
Figure 2.1 Memory Map (2)
43
Figure 2.1 Memory Map (3)
44
Register Configuration
45
Figure 2.2 CPU Registers
45
General Registers
46
Figure 2.3 Usage of General Registers
46
Program Counter (PC)
47
Condition-Code Register (CCR)
47
Figure 2.4 Relationship between Stack Pointer and Stack Area
47
Data Formats
49
General Register Data Formats
49
Figure 2.5 General Register Data Formats (1)
49
Figure 2.5 General Register Data Formats (2)
50
Memory Data Formats
51
Figure 2.6 Memory Data Formats
51
Instruction Set
52
Table of Instructions Classified by Function
52
Table 2.1 Operation Notation
52
Table 2.2 Data Transfer Instructions
53
Table 2.3 Arithmetic Operations Instructions (1)
54
Table 2.3 Arithmetic Operations Instructions (2)
55
Section 2 CPU
56
Table 2.4 Logic Operations Instructions
56
Table 2.5 Shift Instructions
56
Table 2.6 Bit Manipulation Instructions (1)
57
Table 2.6 Bit Manipulation Instructions (2)
58
Table 2.7 Branch Instructions
59
Table 2.8 System Control Instructions
60
Basic Instruction Formats
61
Table 2.9 Block Data Transfer Instructions
61
Addressing Modes and Effective Address Calculation
62
Addressing Modes
62
Figure 2.7 Instruction Formats
62
Table 2.10 Addressing Modes
63
Table 2.11 Absolute Address Access Ranges
64
Figure 2.8 Branch Address Specification in Memory Indirect Mode
65
Effective Address Calculation
66
Table 2.12 Effective Address Calculation (1)
66
Table 2.12 Effective Address Calculation (2)
67
Basic Bus Cycle
68
Access to On-Chip Memory (RAM, ROM)
68
Figure 2.9 On-Chip Memory Access Cycle
68
On-Chip Peripheral Modules
69
Figure 2.10 On-Chip Peripheral Module Access Cycle (3-State Access)
69
CPU States
70
Figure 2.11 CPU Operation States
70
Usage Notes
71
Notes on Data Access to Empty Areas
71
EEPMOV Instruction
71
Bit Manipulation Instruction
71
Figure 2.12 State Transitions
71
Figure 2.13 Example of Timer Configuration with Two Registers Allocated to same Address
72
Section 3 Exception Handling
77
Exception Sources and Vector Address
77
Table 3.1 Exception Sources and Vector Address
77
Register Descriptions
79
Interrupt Edge Select Register 1 (IEGR1)
79
Interrupt Edge Select Register 2 (IEGR2)
80
Interrupt Enable Register 1 (IENR1)
81
Interrupt Flag Register 1 (IRR1)
82
Wakeup Interrupt Flag Register (IWPR)
83
Reset Exception Handling
84
Interrupt Exception Handling
85
External Interrupts
85
Internal Interrupts
86
Interrupt Handling Sequence
86
Figure 3.1 Reset Sequence
86
Interrupt Response Time
88
Figure 3.2 Stack Status after Exception Handling
88
Table 3.2 Interrupt Wait States
88
Figure 3.3 Interrupt Sequence
89
Usage Notes
90
Interrupts after Reset
90
Notes on Stack Area Use
90
Notes on Rewriting Port Mode Registers
90
Figure 3.4 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure
90
Section 4 Address Break
91
Register Descriptions
91
Figure 4.1 Block Diagram of Address Break
91
Address Break Control Register (ABRKCR)
92
Address Break Status Register (ABRKSR)
93
Table 4.1 Access and Data Bus Used
93
Break Address Registers (BARH, BARL)
94
Break Data Registers (BDRH, BDRL)
94
Operation
94
Figure 4.2 Address Break Interrupt Operation Example (1)
95
Figure 4.2 Address Break Interrupt Operation Example (2)
95
Section 5 Clock Pulse Generators
97
Figure 5.1 Block Diagram of Clock Pulse Generators
97
System Clock Generator
98
Connecting Crystal Resonator
98
Figure 5.2 Block Diagram of System Clock Generator
98
Figure 5.3 Typical Connection to Crystal Resonator
98
Figure 5.4 Equivalent Circuit of Crystal Resonator
98
Connecting Ceramic Resonator
99
External Clock Input Method
99
Figure 5.5 Typical Connection to Ceramic Resonator
99
Figure 5.6 Example of External Clock Input
99
Table 5.1 Crystal Resonator Parameters
99
Subclock Generator
100
Connecting 32.768-Khz Crystal Resonator
100
Figure 5.7 Block Diagram of Subclock Generator
100
Figure 5.8 Typical Connection to 32.768-Khz Crystal Resonator
100
Figure 5.9 Equivalent Circuit of 32.768-Khz Crystal Resonator
100
Pin Connection When Not Using Subclock
101
Prescalers
101
Prescaler W
101
Figure 5.10 Pin Connection When Not Using Subclock
101
Usage Notes
102
Note on Resonators
102
Notes on Board Design
102
Figure 5.11 Example of Incorrect Board Design
102
Section 6 Power-Down Modes
103
Register Descriptions
103
System Control Register 1 (SYSCR1)
104
Table 6.1 Operating Frequency and Waiting Time
105
System Control Register 2 (SYSCR2)
106
Module Standby Control Register 1 (MSTCR1)
107
Mode Transitions and States of LSI
108
Figure 6.1 Mode Transition Diagram
108
Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling
109
Table 6.3 Internal State in each Operating Mode
110
Sleep Mode
111
Standby Mode
111
Subsleep Mode
111
Subactive Mode
112
Operating Frequency in Active Mode
112
Direct Transition
113
Direct Transition from Active Mode to Subactive Mode
113
Direct Transition from Subactive Mode to Active Mode
113
Module Standby Function
114
Section 7 ROM
115
Block Configuration
115
Figure 7.1 Flash Memory Block Configuration
116
Register Descriptions
116
Erase Block Register 1 (EBR1)
116
Flash Memory Control Register 1 (FLMCR1)
117
Flash Memory Control Register 2 (FLMCR2)
118
Erase Block Register 1 (EBR1)
119
Flash Memory Power Control Register (FLPWCR)
120
Flash Memory Enable Register (FENR)
120
On-Board Programming Modes
121
Boot Mode
121
Table 7.1 Setting Programming Modes
121
Table 7.2 Boot Mode Operation
123
Programming/Erasing in User Program Mode
124
Table 7.3 System Clock Frequencies for Which Automatic Adjustment of LSI Bit Rate Is Possible
124
Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode
125
Flash Memory Programming/Erasing
126
Program/Program-Verify
126
Figure 7.3 Program/Program-Verify Flowchart
127
Erase/Erase-Verify
128
Table 7.4 Reprogram Data Computation Table
128
Table 7.5 Additional-Program Data Computation Table
128
Table 7.6 Programming Time
128
Interrupt Handling When Programming/Erasing Flash Memory
129
Figure 7.4 Erase/Erase-Verify Flowchart
130
Program/Erase Protection
131
Hardware Protection
131
Software Protection
131
Error Protection
131
Programmer Mode
132
Power-Down States for Flash Memory
132
Table 7.7 Flash Memory Operating States
133
Section 8 RAM
135
Section 9 I/O Ports
137
Port 1
137
Figure 9.1 Port 1 Pin Configuration
137
Port Mode Register 1 (PMR1)
138
Port Control Register 1 (PCR1)
139
Port Data Register 1 (PDR1)
139
Port Pull-Up Control Register 1 (PUCR1)
140
Pin Functions
140
Port 2
142
Figure 9.2 Port 2 Pin Configuration
142
Port Control Register 2 (PCR2)
143
Port Data Register 2 (PDR2)
143
Pin Functions
144
Port 5
145
Figure 9.3 Port 5 Pin Configuration
145
Port Mode Register 5 (PMR5)
146
Port Control Register 5 (PCR5)
147
Port Data Register 5 (PDR5)
147
Port Pull-Up Control Register 5 (PUCR5)
148
Pin Functions
148
Port 7
151
Figure 9.4 Port 7 Pin Configuration
151
Port Control Register 7 (PCR7)
152
Port Data Register 7 (PDR7)
152
Pin Functions
153
Port 8
154
Port Control Register 8 (PCR8)
154
Figure 9.5 Port 8 Pin Configuration
154
Port Data Register 8 (PDR8)
155
Pin Functions
155
Port B
158
Port Data Register B (PDRB)
158
Figure 9.6 Port B Pin Configuration
158
Section 10 Timer a
159
Features
159
Input/Output Pins
160
Figure 10.1 Block Diagram of Timer a
160
Table 10.1 Pin Configuration
160
Register Descriptions
161
Timer Mode Register a (TMA)
161
Timer Counter a (TCA)
162
Operation
163
Interval Timer Operation
163
Clock Time Base Operation
163
Clock Output
163
Usage Note
163
Section 11 Timer V
165
Features
165
Input/Output Pins
166
Figure 11.1 Block Diagram of Timer V
166
Table 11.1 Pin Configuration
166
Register Descriptions
167
Timer Counter V (TCNTV)
167
Time Constant Registers a and B (TCORA, TCORB)
167
Timer Control Register V0 (TCRV0)
168
Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions
169
Timer Control/Status Register V (TCSRV)
170
Timer Control Register V1 (TCRV1)
171
Operation
172
Timer V Operation
172
Figure 11.2 Increment Timing with Internal Clock
173
Figure 11.3 Increment Timing with External Clock
173
Figure 11.4 OVF Set Timing
173
Figure 11.5 CMFA and CMFB Set Timing
174
Figure 11.6 TMOV Output Timing
174
Figure 11.7 Clear Timing by Compare Match
174
Figure 11.8 Clear Timing by TMRIV Input
175
Timer V Application Examples
176
Pulse Output with Arbitrary Duty Cycle
176
Figure 11.9 Pulse Output Example
176
Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input
177
Figure 11.10 Example of Pulse Output Synchronized to TRGV Input
177
Usage Notes
178
Figure 11.11 Contention between TCNTV Write and Clear
178
Figure 11.12 Contention between TCORA Write and Compare Match
179
Figure 11.13 Internal Clock Switching and TCNTV Operation
179
Section 12 Timer W
181
Features
181
Table 12.1 Timer W Functions
182
Figure 12.1 Timer W Block Diagram
183
Input/Output Pins
184
Register Descriptions
184
Table 12.2 Pin Configuration
184
Timer Mode Register W (TMRW)
185
Timer Control Register W (TCRW)
186
Timer Interrupt Enable Register W (TIERW)
187
Timer Status Register W (TSRW)
188
Timer I/O Control Register 0 (TIOR0)
189
Timer I/O Control Register 1 (TIOR1)
191
Timer Counter (TCNT)
192
General Registers a to D (GRA to GRD)
192
Operation
193
Normal Operation
193
Figure 12.2 Free-Running Counter Operation
194
Figure 12.3 Periodic Counter Operation
194
Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1)
195
Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1)
195
Figure 12.6 Toggle Output Example (TOA = 0, TOB = 1)
195
Figure 12.7 Input Capture Operating Example
196
PWM Operation
197
Figure 12.8 Buffer Operation Example (Input Capture)
197
Figure 12.9 PWM Mode Example (1)
198
Figure 12.10 PWM Mode Example (2)
198
Figure 12.11 Buffer Operation Example (Output Compare)
199
Figure 12.12 PWM Mode Example (TOB, TOC, and TOD = 0: Initial Output Values Are Set to 0)
200
Figure 12.13 PWM Mode Example (TOB, TOC, and TOD = 1: Initial Output Values Are Set to 1)
201
Operation Timing
202
TCNT Count Timing
202
Output Compare Output Timing
202
Figure 12.14 Count Timing for Internal Clock Source
202
Figure 12.15 Count Timing for External Clock Source
202
Input Capture Timing
203
Figure 12.16 Output Compare Output Timing
203
Figure 12.17 Input Capture Input Signal Timing
203
Timing of Counter Clearing by Compare Match
204
Buffer Operation Timing
204
Figure 12.18 Timing of Counter Clearing by Compare Match
204
Figure 12.19 Buffer Operation Timing (Compare Match)
204
Timing of IMFA to IMFD Flag Setting at Compare Match
205
Figure 12.20 Buffer Operation Timing (Input Capture)
205
Figure 12.21 Timing of IMFA to IMFD Flag Setting at Compare Match
205
Timing of IMFA to IMFD Setting at Input Capture
206
Timing of Status Flag Clearing
206
Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture
206
Figure 12.23 Timing of Status Flag Clearing by CPU
206
Usage Notes
207
Figure 12.24 Contention between TCNT Write and Clear
207
Figure 12.25 Internal Clock Switching and TCNT Operation
208
Figure 12.26 When Compare Match and Bit Manipulation Instruction to TCRW Occur at the same Timing
209
Section 13 Watchdog Timer
211
Features
211
Figure 13.1 Block Diagram of Watchdog Timer
211
Register Descriptions
212
Timer Control/Status Register WD (TCSRWD)
212
Timer Counter WD (TCWD)
213
Timer Mode Register WD (TMWD)
214
Operation
215
Figure 13.2 Watchdog Timer Operation Example
215
Section 14 Serial Communication Interface 3 (SCI3)
217
Features
217
Figure 14.1 Block Diagram of SCI3
218
Input/Output Pins
219
Register Descriptions
219
Table 14.1 Pin Configuration
219
Receive Shift Register (RSR)
220
Receive Data Register (RDR)
220
Transmit Shift Register (TSR)
220
Transmit Data Register (TDR)
220
Serial Mode Register (SMR)
221
Serial Control Register 3 (SCR3)
222
Serial Status Register (SSR)
224
Bit Rate Register (BRR)
226
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
227
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
228
Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
229
Table 14.3 Maximum Bit Rate for each Frequency (Asynchronous Mode)
230
Table 14.4 Examples of BBR Setting for Various Bit Rates
231
Table 14.4 Examples of BRR Settings for Various Bit Rates
232
Operation in Asynchronous Mode
233
Clock
233
Figure 14.2 Data Format in Asynchronous Communication
233
Figure 14.3 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits)
233
SCI3 Initialization
234
Figure 14.4 Sample SCI3 Initialization Flowchart
234
Data Transmission
235
Figure 14.5 Example SCI3 Operation in Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
235
Figure 14.6 Sample Serial Transmission Flowchart (Asynchronous Mode)
236
Serial Data Reception
237
Figure 14.7 Example SCI3 Operation in Reception in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit)
237
Table 14.5 SSR Status Flags and Receive Data Handling
238
Figure 14.8 Sample Serial Data Reception Flowchart (Asynchronous Mode) (1)
239
Figure 14.8 Sample Serial Reception Data Flowchart (2)
240
Operation in Clocked Synchronous Mode
241
Clock
241
SCI3 Initialization
241
Figure 14.9 Data Format in Clocked Synchronous Communication
241
Serial Data Transmission
242
Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode
243
Figure 14.11 Sample Serial Transmission Flowchart (Clocked Synchronous Mode)
244
Serial Data Reception (Clocked Synchronous Mode)
245
Figure 14.12 Example of SCI3 Reception Operation in Clocked Synchronous Mode
245
Figure 14.13 Sample Serial Reception Flowchart (Clocked Synchronous Mode)
246
Simultaneous Serial Data Transmission and Reception
247
Figure 14.14 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations (Clocked Synchronous Mode)
248
Multiprocessor Communication Function
249
Multiprocessor Serial Data Transmission
250
Figure 14.15 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
250
Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart
251
Multiprocessor Serial Data Reception
252
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (1)
253
Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2)
254
Figure 14.18 Example of SCI3 Operation in Reception Using Multiprocessor Format (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
255
Interrupts
256
Table 14.6 SCI3 Interrupt Requests
256
Usage Notes
257
Break Detection and Processing
257
Mark State and Break Sending
257
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
257
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
258
Figure 14.19 Receive Data Sampling Timing in Asynchronous Mode
258
Section 15 I C Bus Interface 2 (IIC2)
259
Features
259
Figure 15.1 Block Diagram of I
260
Input/Output Pins
261
Register Descriptions
261
Figure 15.2 External Circuit Connections of I/O Pins
261
C Bus Control Register 1 (ICCR1)
262
Table 15.2 Transfer Rate
263
C Bus Control Register 2 (ICCR2)
264
C Bus Mode Register (ICMR)
265
C Bus Interrupt Enable Register (ICIER)
267
C Bus Status Register (ICSR)
269
Slave Address Register (SAR)
272
C Bus Transmit Data Register (ICDRT)
273
C Bus Receive Data Register (ICDRR)
273
C Bus Shift Register (ICDRS)
273
Operation
274
C Bus Format
274
Figure 15.3 I 2 C Bus Formats
274
Figure 15.4 I 2 C Bus Timing
274
Master Transmit Operation
275
Figure 15.5 Master Transmit Mode Operation Timing (1)
276
Figure 15.6 Master Transmit Mode Operation Timing (2)
276
Master Receive Operation
277
Figure 15.7 Master Receive Mode Operation Timing (1)
278
Slave Transmit Operation
279
Figure 15.8 Master Receive Mode Operation Timing (2)
279
Figure 15.9 Slave Transmit Mode Operation Timing (1)
280
Slave Receive Operation
281
Figure 15.10 Slave Transmit Mode Operation Timing (2)
281
Figure 15.11 Slave Receive Mode Operation Timing (1)
282
Figure 15.12 Slave Receive Mode Operation Timing (2)
282
Clocked Synchronous Serial Format
283
Figure 15.13 Clocked Synchronous Serial Transfer Format
283
Figure 15.14 Transmit Mode Operation Timing
284
Noise Canceler
285
Figure 15.15 Receive Mode Operation Timing
285
Figure 15.16 Block Diagram of Noise Conceler
285
Example of Use
286
Figure 15.17 Sample Flowchart for Master Transmit Mode
286
Figure 15.18 Sample Flowchart for Master Receive Mode
287
Figure 15.19 Sample Flowchart for Slave Transmit Mode
288
Figure 15.20 Sample Flowchart for Slave Receive Mode
289
Interrupt Request
290
Table 15.3 Interrupt Requests
290
Bit Synchronous Circuit
291
Figure 15.21 the Timing of the Bit Synchronous Circuit
291
Table 15.4 Time for Monitoring SCL
291
Usage Notes
292
Issue (Retransmission) of Start/Stop Conditions
292
WAIT Setting in I
292
C Bus Mode Register (ICMR)
292
Section 16 A/D Converter
293
Features
293
Figure 16.1 Block Diagram of A/D Converter
294
Input/Output Pins
295
Table 16.1 Pin Configuration
295
Register Descriptions
296
A/D Data Registers a to D (ADDRA to ADDRD)
296
Table 16.2 Analog Input Channels and Corresponding ADDR Registers
296
A/D Control/Status Register (ADCSR)
297
A/D Control Register (ADCR)
298
Operation
299
Single Mode
299
Scan Mode
299
Input Sampling and A/D Conversion Time
300
Figure 16.2 A/D Conversion Timing
300
External Trigger Input Timing
301
Figure 16.3 External Trigger Input Timing
301
Table 16.3 A/D Conversion Time (Single Mode)
301
A/D Conversion Accuracy Definitions
302
Figure 16.4 A/D Conversion Accuracy Definitions (1)
303
Figure 16.5 A/D Conversion Accuracy Definitions (2)
303
Usage Notes
304
Permissible Signal Source Impedance
304
Influences on Absolute Accuracy
304
Figure 16.6 Analog Input Circuit Example
304
Section 17 EEPROM
305
Features
305
Figure 17.1 Block Diagram of EEPROM
306
Input/Output Pins
307
Register Description
307
EEPROM Key Register (EKR)
307
Table 17.1 Pin Configuration
307
Operation
308
EEPROM Interface
308
Bus Format and Timing
308
Start Condition
308
Figure 17.2 EEPROM Bus Format and Bus Timing
308
Stop Condition
309
Acknowledge
309
Slave Addressing
309
Table 17.2 Slave Addresses
310
Write Operations
311
Figure 17.3 Byte Write Operation
311
Acknowledge Polling
312
Figure 17.4 Page Write Operation
312
Read Operation
313
Figure 17.5 Current Address Read Operation
313
Sequential Read
314
Figure 17.6 Random Address Read Operation
314
Figure 17.7 Sequential Read Operation (When Current Address Read Is Used)
315
Usage Notes
316
Data Protection at V
316
On/Off
316
Write/Erase Endurance
316
Noise Suppression Time
316
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional)
317
Features
317
Register Descriptions
318
Low-Voltage-Detection Control Register (LVDCR)
318
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Figure 18.1 Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit
318
Low-Voltage-Detection Status Register (LVDSR)
320
Table 18.1 LVDCR Settings and Select Functions
320
Operation
321
Power-On Reset Circuit
321
Low-Voltage Detection Circuit
322
Figure 18.2 Operational Timing of Power-On Reset Circuit
322
Figure 18.3 Operational Timing of LVDR Circuit
323
Figure 18.4 Operational Timing of LVDI Circuit
324
Figure 18.5 Timing for Operation/Release of Low-Voltage Detection Circuit
325
Section 19 Power Supply Circuit
327
When Using Internal Power Supply Step-Down Circuit
327
Figure 19.1 Power Supply Connection When Internal Step-Down Circuit Is Used
327
When Not Using Internal Power Supply Step-Down Circuit
328
Figure 19.2 Power Supply Connection When Internal Step-Down Circuit Is Not Used
328
Section 20 List of Registers
329
Register Addresses (Address Order)
330
Register Bits
335
Registers States in each Operating Mode
339
Section 21 Electrical Characteristics
343
Absolute Maximum Ratings
343
Electrical Characteristics
343
Power Supply Voltage and Operating Ranges
343
Version)
343
Table 21.1 Absolute Maximum Ratings
343
DC Characteristics
346
Table 21.2 DC Characteristics (1)
346
Table 21.2 DC Characteristics (2)
350
Table 21.2 DC Characteristics (3)
351
AC Characteristics
352
Table 21.3 AC Characteristics
352
Table 21.4 I 2 C Bus Interface Timing
354
Table 21.5 Serial Communication Interface (SCI) Timing
355
A/D Converter Characteristics
356
Table 21.6 A/D Converter Characteristics
356
Watchdog Timer Characteristics
357
Table 21.7 Watchdog Timer Characteristics
357
Flash Memory Characteristics
358
Table 21.8 Flash Memory Characteristics
358
EEPROM Characteristics
360
Table 21.9 EEPROM Characteristics
360
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
361
Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics
361
Power-On Reset Circuit Characteristics (Optional)
362
Electrical Characteristics (Mask-ROM Version, EEPROM Stacked Mask-ROM Version)
362
Power Supply Voltage and Operating Ranges
362
Table 21.11 Power-On Reset Circuit Characteristics
362
DC Characteristics
365
Table 21.12 DC Characteristics (1)
365
Table 21.12 DC Characteristics (2)
369
Table 21.12 DC Characteristics (3)
370
AC Characteristics
371
Table 21.13 AC Characteristics
371
Table 21.14 I 2 C Bus Interface Timing
373
Table 21.15 Serial Communication Interface (SCI) Timing
374
A/D Converter Characteristics
375
Table 21.16 A/D Converter Characteristics
375
Watchdog Timer Characteristics
376
Table 21.17 Watchdog Timer Characteristics
376
EEPROM Characteristics
377
Table 21.18 EEPROM Characteristics
377
Power-Supply-Voltage Detection Circuit Characteristics (Optional)
378
Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics
378
Power-On Reset Circuit Characteristics (Optional)
379
Operation Timing
379
Figure 21.1 System Clock Input Timing
379
Table 21.20 Power-On Reset Circuit Characteristics
379
Figure 21.2 RES Low Width Timing
380
Figure 21.3 Input Timing
380
Figure 21.4 I C Bus Interface Input/Output Timing
380
Figure 21.5 SCK3 Input Clock Timing
381
Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode
381
Output Load Condition
382
Figure 21.7 EEPROM Bus Timing
382
Figure 21.8 Output Load Circuit
382
Appendix A Instruction Set
383
Instruction List
383
Table A.1 Instruction Set
385
Arithmetic Instructions
387
Logic Instructions
390
Shift Instructions
391
Bit-Manipulation Instructions
392
Branching Instructions
394
System Control Instructions
396
Operation Code Map
398
Table A.2 Operation Code Map (1)
398
Table A.2 Operation Code Map (2)
399
Table A.2 Operation Code Map (3)
400
Number of Execution States
401
Table A.3 Number of Cycles in each Instruction
402
Table A.4 Number of Cycles in each Instruction
403
Combinations of Instructions and Addressing Modes
412
Table A.5 Combinations of Instructions and Addressing Modes
412
Appendix B I/O Port Block Diagrams
413
I/O Port Block Diagrams
413
Figure B.1 Port 1 Block Diagram (P17)
413
Figure B.2 Port 1 Block Diagram (P16 to P14)
414
Figure B.3 Port 1 Block Diagram (P12, P11)
415
Figure B.4 Port 1 Block Diagram (P10)
416
Figure B.5 Port 2 Block Diagram (P22)
417
Figure B.6 Port 2 Block Diagram (P21)
418
Figure B.7 Port 2 Block Diagram (P20)
419
Figure B.8 Port 5 Block Diagram (P57, P56)
420
Figure B.9 Port 5 Block Diagram (P55)
421
Figure B.10 Port 5 Block Diagram (P54 to P50)
422
Figure B.11 Port 7 Block Diagram (P76)
423
Figure B.12 Port 7 Block Diagram (P75)
424
Figure B.13 Port 7 Block Diagram (P74)
425
Figure B.14 Port 8 Block Diagram (P87 to P85)
426
Figure B.15 Port 8 Block Diagram (P84 to P81)
427
Figure B.16 Port 8 Block Diagram (P80)
428
Port States in each Operating State
429
Figure B.17 Port B Block Diagram (PB7 to PB0)
429
Appendix C Product Code Lineup
430
Appendix D Package Dimensions
433
Figure D.1 FP-64E Package Dimensions
433
Figure D.2 FP-64A Package Dimensions
434
Figure D.3 FP-48F Package Dimensions
435
Figure D.4 FP-48B Package Dimensions
436
Figure D.5 TNP-48 Package Dimensions
437
Appendix E EEPROM Stacked-Structure Cross-Sectional View
438
Figure E.1 EEPROM Stacked-Structure Cross-Sectional View
438
Main Revisions and Additions in this Edition
439
Section 6 Power-Down Modes
440
Section 13 Watchdog
440
Section 11 Timer
440
Section 15 I
441
Section 16 A/D Converter
441
Section 18 Power-On
441
Section 21 Electrical Characteristics
441
Appendix D Package Dimensions
442
Index
443
Section 10 Timer a
446
Section 11 Timer
446
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