Qorvo PAC5556 Manuals

Manuals and User Guides for Qorvo PAC5556. We have 1 Qorvo PAC5556 manual available for free PDF download: User Manual

Qorvo PAC5556 User Manual (126 pages)

Brand: Qorvo | Category: Controller | Size: 1.32 MB

Table of Contents
2
Overview
11
Style and Formatting Conventions
12
Number Representation
12
Formatting Styles
12
Architectural Block Diagram
13
Figure 3-1 PAC5556 Architectural Block Diagram
13
Info2 Flash Memory Map
14
Analog Register Access
15
Overview
15
Functional Description
15
Figure 5-1 PAC5556 Register Access
15
USART Configuration
16
Protocol
16
Write Register Example
16
Read Register Example
17
Figure 5-2 Analog Peripheral Register Write Timing
17
Figure 5-3 Analog Peripheral Register Read Timing
17
Pac5556 Io
18
Overview
18
Figure 6-1 GPIO and DPM Block Diagram
18
ADC Channels
19
Table 6-1 PAC5556 ADC Input Pins
19
Digital Peripheral Pins
20
Table 6-2 PAC5556 Digital Peripheral Pins
20
PAC5556 ADC Muxes
22
System Block Diagram
22
Figure 7-1 PAC5556 ADC MUX Inputs
22
Adc Mux
23
Afe Mux
23
Table 7-1 PAC5556 ADC MUX Channels
23
Pwrmon Mux
25
Table 7-2 PAC5556 ADC MUX Channels
25
Table 7-3 PAC5556 ADC MUX Channels
26
Emux
27
Figure 8-1 EMUX Timing Diagram
28
Configurable Power Manager
29
Features
29
System Block Diagram
29
Figure 9-1 CPM System Block Diagram
29
Functional Description
30
High-Voltage Buck (HV-BUCK)
30
VP Low Warning
30
Power Manager Faults
31
Temperature Warnings and Faults
32
Register Summary
33
Table 9-1 CPM Register Summary
33
Register Detail
34
Soc.fault
34
Register 9-1 SOC.FAULT (Fault Condition, 00H)
34
Soc.status
35
Register 9-2 SOC.STATUS (System Status, 01H)
35
Soc.misc
36
Register 9-3 SOC.MISC (SOC Miscellaneous Configuration, 02H)
36
Soc.pwrctl
37
Register 9-4 SOC.PWRCTL (Power Control, 03H)
37
Soc.faultenable
38
Register 9-5 SOC.FAULTENABLE (Fault Mask, 04H)
38
Soc.watchdog
39
Register 9-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05H)
39
Soc.sysconf
40
Register 9-7 SOC.SYSCONF (System Configuration, 2Bh)
40
Configurable Analog Front-End
41
Features
41
System Block Diagram
42
Figure 10-1 CAFE System Block Diagram
42
Functional Description
43
Enabling the CAFE
43
Entering Hibernate Mode
43
Hibernate Wake-Up Using the Wake-Up Timer
43
Hibernate Wake-Up Using Push-Button
44
DAC Output
44
VREF Output
44
Aio10
46
System Block Diagram
47
Figure 10-2 AIO10 Block Diagram
47
AIO1, AIO0 Digital I/O Mode
48
AIO1, AIO0 Differential Amplifier Mode
48
Aio32
51
System Block Diagram
52
Figure 10-3 AIO32 Block Diagram
52
AIO3, AIO2 Digital I/O Mode
53
AIO3, AIO2 Differential Amplifier Mode
53
Aio54
56
System Block Diagram
57
Figure 10-4 AIO54 Block Diagram
57
AIO5, AIO4 Digital I/O Mode
58
AIO4, AIO5 Differential Amplifier Mode
58
Aio6
61
System Block Diagram
62
Figure 10-5 AIO6 System Block Diagram
62
AIO6 Digital I/O Mode
63
AIO6 Amplifier Mode
63
AIO6 Comparator Mode
63
AIO6 Special Mode
64
Aio7
65
System Block Diagram
66
Figure 10-6 AIO7 System Block Diagram
66
AIO7 Digital I/O Mode
68
AIO7 Amplifier Mode
68
AIO7 Comparator Mode
68
AIO7 Special Mode
69
Aio8
72
System Block Diagram
73
Figure 10-7 AIO8 System Block Diagram
73
AIO8 Digital I/O Mode
74
AIO8 Amplifier Mode
74
AIO8 Comparator Mode
74
Comparator Reference
74
AIO8 Special Mode
75
Aio9
78
System Block Diagram
79
Figure 10-8 AIO9 System Block Diagram
79
AIO9 Digital I/O Mode
80
AIO9 Amplifier Mode
80
AIO9 Special Mode
82
Register Summary
84
Table 10-1 CAFE Register Summary
84
Register Detail
85
Soc.cfgaio0
85
Register 10-1 SOC.CFGAIO0 (AIO0 Configuration, 06H)
85
Soc.cfgaio1
86
Register 10-2 SOC.CFGAIO1 (AIO1 Configuration, 07H)
86
Soc.cfgaio2
87
Register 10-3 SOC.CFGAIO2 (AIO2 Configuration, 08H)
87
Soc.cfgaio3
88
Register 10-4 SOC.CFGAIO3 (AIO3 Configuration, 09H)
88
Soc.cfgaio4
89
Register 10-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)
89
Soc.cfgaio5
90
Register 10-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)
90
Soc.cfgaio6
91
Register 10-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch)
91
Soc.cfgaio7
92
Register 10-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh)
92
Soc.cfgaio8
93
Register 10-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)
93
Soc.cfgaio9
94
Register 10-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)
94
Soc.sigset
95
Register 10-11 SOC.SIGSET (Signal Manager Configuration, 10H)
95
Soc.hpdach
96
Soc.hpdacl
96
Soc.lpdach
96
Soc.lpdacl
96
Register 10-12 SOC.HPDACH (HPDAC High Setting, 11H)
96
Register 10-13 SOC.HPDACL (HPDAC Low Setting, 12H)
96
Register 10-14 SOC.LPDACH (LPDAC High Setting, 13H)
96
Register 10-15 SOC.LPDAC1 (LPDAC Low Setting, 14H)
96
Soc.shcfg1
97
Register 10-16 SOC.SHCFG1 (Sample and Hold Configuration, 15H)
97
Soc.shcfg2
98
Register 10-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16H)
98
Soc.protinten
99
Register 10-18 SOC.PROTINTEN (Protection Interrupt Enable, 17H)
99
Soc.protstat
100
Register 10-19 SOC.PROTSTAT (Protection Interrupt Status, 18H)
100
Soc.doutsig0
101
Soc.doutsig1
101
Register 10-20 SOC.DOUTSIG0 (Digital Output 0, 19H)
101
Register 10-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)
101
Soc.dinsig0
102
Soc.dinsig1
102
Register 10-22 SOC.DINSIG0 (Digital Input 0, 1Bh)
102
Register 10-23 SOC.DINSIG1 (Digital Input 1, 1Ch)
102
Soc.cfgio1
103
Register 10-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)
103
Soc.siginten
104
Register 10-25 SOC.SIGINTEN (AIO Interrupt Enable Configuration, 1Fh)
104
Soc.sigintf
105
Register 10-26 SOC.SIGINTF (AIO Interrupt Flag, 20H)
105
Soc.blanking
106
Register 10-27 SOC.BLANKING (Comparator Blanking Configuration, 21H)
106
Soc.speccfg0
107
Register 10-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22H)
107
Soc.speccfg1
108
Register 10-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23H)
108
Soc.speccfg2
109
Register 10-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24H)
109
Soc.speccfg3
110
Register 10-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25H)
110
Application Specific Power Driver
111
Features
111
System Block Diagram
112
Figure 11-1 ASPD System Block Diagram
112
Functional Description
113
High-Side Gate Drivers
113
Figure 11-2 ASPD High-Side Gate Drivers
113
Low-Side Gate Drivers
114
Figure 11-3 ASPD Low-Side Gate Drivers
114
Figure 11-3 Cycle by Cycle Current Limit
116
Table 11-1 ASPD Register Summary
119
Register 11-1 SOC.CFGDRV1 (Driver Configuration 1, 27H)
120
Register 11-2 SOC.CFGDRV2 (Driver Configuration 2, 28H)
121
Register 11-3 SOC.CFGDRV3 (Driver Configuration 3, 29H)
122
Register 11-4 SOC.STATDRV (Driver Status, 2Ah)
123
Register 11-5 SOC.CFGDRV4 (Driver Configuration 4, 7Bh)
124
Register 11-6 SOC.DRV_FLT (Driver Fault Flag, 7Ch)
124
Register 11-7 SOC.ENDRV (Driver Manager Enable, 7Dh)
124
Register 11-8 SOC.WDTPASS (WDT Password, 7Eh)
125

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Qorvo PAC5556 User Manual (126 pages)

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