Qorvo PAC5556 User Manual
  1. Manuals
  2. Brands
  3. Qorvo Manuals
  4. Controller
  5. PAC5556
  6. User manual

Qorvo PAC5556 User Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Download this manual
®
Power Application Controller
PAC5556 Device User Guide
®
Power Application Controller
TM
Configurable Analog Front End
TM
Application Specific Power Drivers
®
®
Arm
Cortex
-M4F Controller Core
-1-
©
Copyright
2020 Qorvo, Inc.
Rev 2.2 – Nov 25, 2020

Advertisement

Table of Contents
loading

Related Manuals for Qorvo PAC5556

Summary of Contents for Qorvo PAC5556

  • Page 1 ® Power Application Controller PAC5556 Device User Guide ® Power Application Controller Configurable Analog Front End Application Specific Power Drivers ® ® Cortex -M4F Controller Core © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 2: Table Of Contents

    Write Register Example ....................16 Read Register Example ....................17 PAC5556 IO ........................18 Overview ........................18 ADC Channels ......................19 Digital Peripheral Pins ....................20 PAC5556 ADC MUXes ......................22 System Block Diagram ....................22 ADC MUX ........................23 AFE MUX ........................23 PWRMON MUX ......................25 EMUX ..........................27 CONFIGURABLE POWER MANAGER ................29 Features ........................29...
  • Page 3 10.11.2 AIO3, AIO2 Digital I/O Mode ................53 10.11.3 AIO3, AIO2 Differential Amplifier Mode ............53 10.12 AIO54 ........................56 10.12.1 System Block Diagram ..................57 10.12.2 AIO5, AIO4 Digital I/O Mode ................58 © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 4 AIO9 Amplifier Mode ..................80 10.16.4 AIO9 Special Mode ..................82 10.17 Register Summary ....................84 10.18 Register Detail ......................85 10.18.1 SOC.CFGAIO0 ....................85 10.18.2 SOC.CFGAIO1 ....................86 10.18.3 SOC.CFGAIO2 ....................87 10.18.4 SOC.CFGAIO3 ....................88 10.18.5 SOC.CFGAIO4 ....................89 © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 5 APPLICATION SPECIFIC POWER DRIVER ..............111 11.1 Features ........................111 11.2 System Block Diagram ....................112 11.3 Functional Description ....................113 11.4 High-Side Gate Drivers ..................... 113 11.5 Low-Side Gate Drivers ....................114 © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 6 SOC.CFGDRV2 ..................... 121 11.13.3 SOC.CFGDRV3 ..................... 122 11.13.4 SOC.STATDRV ....................123 11.13.5 SOC.CFGDRV4 ..................... 124 11.13.6 SOC.DRV_FLT ....................124 11.13.7 SOC.ENDRV ....................124 11.13.8 SOC.WDTPASS ..................... 125 LEGAL INFORMATION ....................126 © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 7 ® Power Application Controller LIST OF FIGURES Figure 3-1 PAC5556 Architectural Block Diagram ..............13 Figure 5-1 PAC5556 Register Access ..................15 Figure 5-2 Analog Peripheral Register Write Timing ..............17 Figure 5-3 Analog Peripheral Register Read Timing ..............17 Figure 6-1 GPIO and DPM Block Diagram ................18 Figure 7-1 PAC5556 ADC MUX inputs ..................22...
  • Page 8 ® Power Application Controller LIST OF TABLES Table 6-1 PAC5556 ADC Input Pins ..................19 Table 6-2 PAC5556 Digital Peripheral Pins ................20 Table 7-1 PAC5556 ADC MUX channels ..................23 Table 7-2 PAC5556 ADC MUX channels ..................25 Table 7-3 PAC5556 ADC MUX channels ..................26 Table 9-1 CPM Register Summary ....................33...
  • Page 9 Register 10-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) ..... 110 Register 11-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..........120 Register 11-2 SOC.CFGDRV2 (Driver Configuration 2, 28h) ..........121 Register 11-3 SOC.CFGDRV3 (Driver Configuration 3, 29h) ..........122 © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 10 Register 11-5 SOC.CFGDRV4 (Driver Configuration 4, 7Bh) ..........124 Register 11-6 SOC.DRV_FLT (Driver Fault Flag, 7Ch) ............124 Register 11-7 SOC.ENDRV (Driver Manager Enable, 7Dh) ............ 124 Register 11-8 SOC.WDTPASS (WDT Password, 7Eh) ............125 -10- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 11: Overview

    ® Power Application Controller OVERVIEW This document is the PAC5556 Device User Guide. It details the operation of the analog peripherals in the PAC5556. For detailed information on the MCU and Digital Peripherals in the PAC5556, see the PAC55XX Family User Guide.

  • Page 12: Style And Formatting Conventions

    CPU Mnemonic uses monospaced text. CPU Mnemonic Operands use monospaced italic text. {Rd, }, Rn, Rm Operands b loopA Code examples Code examples use monospaced text. -12- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 13: Architectural Block Diagram

    ® Power Application Controller ARCHITECTURAL BLOCK DIAGRAM For Below is an architecture block diagram of the PAC5556 device. Figure 3-1 PAC5556 Architectural Block Diagram PAC5556 Power Application Controller CONFIGURABLE POWER MANAGER PX.Y DEBUG/ HIGH- BST_CHG VOLTAGE CONTROLLER 128kB FLASH (HV-BUCK)

  • Page 14: Info2 Flash Memory Map

    ® Power Application Controller INFO2 FLASH MEMORY MAP -14- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 15: Analog Register Access

    Power Application Controller ANALOG REGISTER ACCESS Overview All analog registers in the PAC5556 are accessible through a SOC bus in the device. Unlike registers in the MCU (SRAM and digital peripheral registers), these analog registers are not memory mapped. The block diagram below shows the different system busses that the MCU uses to access the different system registers.

  • Page 16: Usart Configuration

    Write SSPADAT with the value 23h (11h << 1 | 1b for write transaction) ▪ Write SSPADAT with the value 28h The timing diagram from a write operation is shown below. -16- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 17: Read Register Example

    Figure 5-3 Analog Peripheral Register Read Timing For more information on how to configure the DPM to support the USART A peripheral for communicating with the Analog Registers, see the PAC55XX Family User Guide. -17- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 18: Pac5556 Io

    ADC input. For information on how to configure the IO for each of these situations, see the PAC55XX Family User Guide. The PAC5556 has the following IO pins available for application use: ▪ PA[7:0], PC[6:4] – Reserved for MMPM, ASPD, CAFE ▪...

  • Page 19: Adc Channels

    ® Power Application Controller ADC Channels The ADC channels that are available on the PAC5556 are shown in the table below. Table 6-1 PAC5556 ADC Input Pins ADC Channel IO PIN ADC0 ADC4 ADC5 ADC6 ADC7 Available for sampling channels in the CAFE only -19- ©...

  • Page 20: Digital Peripheral Pins

    ® Power Application Controller Digital Peripheral Pins The digital peripheral functions that are available in the PAC5556 are shown below. Table 6-2 PAC5556 Digital Peripheral Pins GPIOxMUXS.Py PORT 000b 001b 010b 011b 100b 101b 110b 111b GPIOA0 GPIOA1 EMUXD GPIOA2...
  • Page 21 TCPHB USDMOSI CANRXD I2CSCL GPIOF7 TCPWM7 TDPWM7 USDMISO CANTXD I2CSDA For more information on how to configure the DPM for the PAC5556, see the PAC55XX Family User Guide. -21- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 22: Pac5556 Adc Muxes

    ® Power Application Controller PAC5556 ADC MUXes The PAC5556 allows the user to internally monitor the various internal and external analog channels through a series of MUXes on the MCU and AFE. System Block Diagram The various MUXes that are used for signal sampling are shown in the diagram below.

  • Page 23: Adc Mux

    ADC and ADC MUX are done automatically in hardware according the DTSE and ADC configuration. In the PAC5556, there are 4 external pins and one internal ADC channel that may be configured for ADC analog input that are shown in the table below.
  • Page 24 (enabled). The AFE MUX channel may be selected from the EMUX data sent from the DTSE. The channels available on the AFE MUX are shown in the table below. -24- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 25: Pwrmon Mux

    ® Power Application Controller Table 7-2 PAC5556 ADC MUX channels AFE MUX Channel Value Description DAO10 0000b Output of Differential Amplifier for AIO10. DAO32 0001b Output of Differential Amplifier for AIO32. DAO54 0010b Output of Differential Amplifier for AIO54. 0011b Analog bus AB1.

  • Page 26: Table 7-3 Pac5556 Adc Mux Channels

    ® Power Application Controller The channels available on the PWRMON MUX are shown in the table below. Table 7-3 PAC5556 ADC MUX channels Channel SOC.PWRCTL.PWRMON Description VCORE 000b LDO output voltage. CORE VP x 1/10 001b MVBB output voltage, scaled by 1/10.

  • Page 27: Emux

    0110b: AB4 MUXA 0111b: AB5 1000b: AB6 1001b: AB7 1010b: AB8 1011b: AB9 1100b: AB10 (VPTAT) 1101b: AB11 (PWRMON) 1110b: AB12 (VP * 1/10) 1111b: AB13 (VREF * 5/10) -27- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 28: Figure 8-1 Emux Timing Diagram

    3:0 of the EMUX packet. Figure 8-1 EMUX Timing Diagram EMUXC EMUXD HDL2 HDL1 HDL0 MUX3 MUX2 MUX1 MUX0 POS S/H DAOxy S/H MUXA -28- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 29: Configurable Power Manager

    DRIVER VSYS COMP LOGIC VOLTAGE SETTING POWER OK & OVP 2.5V ADC TIMERS POWER LINEAR LINEAR LINEAR LINEAR & TEMP HIBERNATE TEMP THREF +5V_INT VCCIO VCORE VCC33 VCC18 -29- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 30: Functional Description

    IRQ1 signal to the MCU will be de-asserted. During this condition, as soon as VP rises above the power good threshold SOC.STATUS.VPLOW will be set to 0b. -30- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 31: Power Manager Faults

    To reset the fault condition, the corresponding fault bit(s) should be written to a 1b and then the power supplies will be re-started according to the power supply sequence. -31- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 32: Temperature Warnings And Faults

    When the die temperature exceeds the fault threshold of 165°C, the SOC.FAULT.TMPFAULT bit is set to 1b. When this fault occurs, the PAC5556 is forced into hibernate mode and will stay in hibernate mode until the push-button or wake-up timer (if configured) is received.

  • Page 33: Register Summary

    Hardware status condition register SOC.MISC Miscellaneous features register SOC.PWRCTL Power Manager control register SOC.FAULTENABLE Power Manager fault enable register SOC.WATCHDOG SOC Watchdog configuration register SOC.SYSCONF Power Manager system configuration register -33- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 34: Register Detail

    VCC33 fault. Set on fault, and cleared when written to 1b. VCC33FLT 0b: No VCC33 fault 1b: VCC33 fault VCORE fault. Set on fault, and cleared when written to 1b. VCOREFLT 0b: No VCORE fault 1b: VCORE fault -34- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 35: Soc.status

    When set, this will assert the IRQ1 interrupt to the MCU. PBSTAT_LATCH To clear this bit and the IRQ1 interrupt, set this bit to 1b. 0b: Latched push-button not active 1b: Latched push-button active -35- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 36: Soc.misc

    0b: 32ms 1b: 1ms Reserved Signal Manager Enable. This bit is automatically cleared when the reset signal to the MCU is asserted. SMEN 0b: Not enabled 1b: Enabled -36- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 37: Soc.pwrctl

    100b: VSYS x 4/10 101b: VMS 110b: VPTAT 111b: VMS (buffered) Push-button Wake-up Timer: 000b: infinite 001b: 125ms 010b: 250ms WUTIMER 011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s -37- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 38: Soc.faultenable

    LDO Fault Enable (VCCIO, VCC33, VCORE). LDOFLTEN 0b: Not enabled 1b: Enabled Push-button Interrupt Enable. PBINTEN 0b: Not enabled 1b: Enabled VP Low Interrupt Enable. VPINTEN 0b: Not enabled 1b: Enabled -38- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 39: Soc.watchdog

    Watchdog Timer Enable. Cleared during hard reset. WDTEN 0b: disabled 1b: enabled Watch-dog Timer. 000b: 62.5ms 001b: 125ms 010b: 250ms 011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s -39- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 40: Soc.sysconf

    HV-BUCK VP Output Setting. VPSET 0b: 12V 1b: 15V HV-BUCK Switching Frequency Setting. 000b: 25kHz 001b: 37.5kHz 010b: 50kHz HVBK_FREQ 100b 011b: 62.5kHz 100b: 71.4kHz 101b: 83.3kHz 110b: 100kHz 111b: 125kHz -40- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 41: Configurable Analog Front-End

    Two high-speed comparators with protection functions • Phase to phase, phase to center-tap modes • Bi-directional, asymmetric configurable comparator hysteresis • Push-button input for entering/exiting hibernate mode • Integrated VM sampling using ADC -41- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 42: System Block Diagram

    DAxN ADC MUX OFFSET AMPx BUF6 COMPARATOR TEMP MON, REF, CMPx DINx THREF AFE I/O DINx AIOx CONTROL PHASE COMPARATOR DINx PHCx PHASE IRQ2/POS PHASE PUSH PHCx BUTTON -42- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 43: Functional Description

    To wake-up from hibernate mode the user may either use the Hibernate Wake-up Timer or the Push-button function. Before entering hibernate mode, one of these two methods must be configured or the PAC5556 will not be able to exit hibernate mode. 10.6 Hibernate wake-up using the Wake-Up Timer To wake up from hibernate mode using the wake-up timer, set SOC.PWRCTL.WUTIMER to the...

  • Page 44: Hibernate Wake-Up Using Push-Button

    111b 10.7 Hibernate wake-up using Push-Button When the PAC5556 is in hibernate mode, the AIO6 push-button may be used to wake up the device. To enable the push-button wake-up using AIO6, the device must be in AIO6 special mode with the push-button enabled. To configure and enable the push-button mode, set SOC.CFGAIO6.MODE6 = 11b and SOC.MISC.PBEN = 1b.
  • Page 45 ® Power Application Controller -45- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 46: Aio10

    ® Power Application Controller 10.10 AIO10 AIO10 may be configured as digital inputs or as a differential amplifier with protection. -46- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 47: System Block Diagram

    SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO1.HP10EN Gate CFGAIO1.HP10PREN HPROT10 Driver HP10 PROTINTEN.HP10INTEN PROTSTAT.HP10INT HPDAC* IRQ1 SIGINTF.HP10STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -47- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 48: Aio1, Aio0 Digital I/O Mode

    Use SOC.CFGAIO1.CAL10EN to short the inputs of the differential amplifier to allow reading of the amplifier offset. The amplifier gain may be set between 1X and 48X by using SOC.CFGAIO0.GAIN10. -48- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 49 The output of HP10 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.HP10INTEN to 1b. The real-time status can be observed using SOC.SIGINTEN.HP10STAT and the latched interrupt status can be observed using SOC.PROTSTAT.HP10INT. -49- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 50 The output of LP10 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.LP10INTEN to 1b. The real-time status can be observed using SOC.SIGINTEN.LP10STAT and the latched interrupt status can be observed using SOC.PROTSTAT.LP10INT. -50- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 51: Aio32

    ® Power Application Controller 10.11 AIO32 AIO32 may be configured as digital inputs or as a differential amplifier with protection. -51- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 52: System Block Diagram

    SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO3.HP32EN Gate CFGAIO3.HP32PREN HPROT32 Driver HP32 PROTINTEN.HP32INTEN PROTSTAT.HP32INT HPDAC* IRQ1 SIGINTF.HP32STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -52- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 53: Aio3, Aio2 Digital I/O Mode

    SOC.SHCFG1.EMUXEN to 0b. In either ADC automatic or manual mode, the ADC buffer must be enabled by setting SOC.SHCFG1.ADCBUFEN to 1b before sampling using the ADC. -53- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 54 SOC.LPDACL. SOC.CFGAIO2.LP32EN may be used to enable LP32 comparator with different blanking times. Set SOC.SIGSET.LPROTHYS to 1b to enable LP32 comparator hysteresis. The output of LP32 comparator can be configured to trigger protection signal PR using SOC.CFGAIO3.LP32PREN. -54- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 55 The output of LP32 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.LP32INTEN to 1b. The real-time status can be observed using SOC.SIGINTEN.LP32STAT and the latched interrupt status can be observed using SOC.PROTSTAT.LP32INT. -55- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 56: Aio54

    ® Power Application Controller 10.12 AIO54 AIO54 may be configured as digital inputs or as a differential amplifier with protection. -56- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 57: System Block Diagram

    SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO5.HP54EN Gate CFGAIO5.HP54PREN HPROT54 Driver HP54 PROTINTEN.HP54INTEN PROTSTAT.HP54INT HPDAC* IRQ1 SIGINTF.HP54STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -57- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 58: Aio5, Aio4 Digital I/O Mode

    SOC.SHCFG1.EMUXEN to 0b. In either ADC automatic or manual mode, the ADC buffer must be enabled by setting SOC.SHCFG1.ADCBUFEN to 1b before sampling using the ADC. -58- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 59 SOC.LPDACL. SOC.CFGAIO5.LP54EN may be used to enable LP54 comparator with different blanking times. Set SOC.SIGSET.LPROTHYS to 1b to enable LP54 comparator hysteresis. The output of LP54 comparator can be configured to trigger protection signal PR using SOC.CFGAIO5.LP54PREN. -59- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 60 The output of LP54 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.LP54INTEN to 1b. The real-time status can be observed using SOC.PROTSTAT.LP54STAT and the latched interrupt status can be observed using SOC.PROTSTAT.LP54INT. -60- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 61: Aio6

    AIO6 may be configured as a digital input, single-ended programmable gain amplifier, comparator, output from analog ABUS or as a push-button input to wake up the device from total hibernate mode. -61- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 62: System Block Diagram

    SIGINTF.AIO6INT CFGAIO6.OPT6 SIGINTEN.AIO6REINTEN SIGINTEN.AIO6FEINTEN AIO6 Special Mode ABUS CFGAIO6.MUX6 CFGAIO6.ADMUX CFGAIO6.MODE6 CFGAIO6.SWAP AMUX AIO6 Push Button Mode PB Wake Up IRQ1 STATUS.PBSTAT STATUS.PBSTAT_LATCH MISC.PBEN Wake-up Power MISC.TPBD Manager -62- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 63: Aio6 Digital I/O Mode

    • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V The output polarity of the comparator may be selected by using SOC.CFGAIO6.POL6 (0b: active-high; 1b: active-low). -63- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 64: Aio6 Special Mode

    To configure the ABUS input to the AIO6 special mode buffer (AB1 – AB7), use SOC.CFGAIO6.MUX6. The SOC.CFGAIO6.SWAP to 1b to swap the random offset of the buffer for calibration. -64- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 65: Aio7

    ® Power Application Controller 10.14 AIO7 AIO7 may be configured as a digital input/output, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -65- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 66: System Block Diagram

    ® Power Application Controller 10.14.1 System Block Diagram Figure 10-6 AIO7 System Block Diagram -66- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 67 CFGAIO9.MODE9[1] CFGAIO9.MUX9[0] CFGAIO8.OPT8[0] CFGAIO8.OPT8[1] CMP Polarity AB<3:1> IRQ2/POS ABUS CFGAIO7.POL7 AIO8 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN7 SPECCFG2.SMUXAIO7 SIGINTF.AIO7INT SIGINTEN.AIO7REINTEN BLANKING.BLANKTIME BLANKING.BLANKMODE SIGINTEN.AIO7FEINTEN SPECCFG0.HYSMODE SPECCFG0.AIO7HYS CFGAIO7.MODE7 EMUX IRQ2 -67- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 68: Aio7 Digital I/O Mode

    (VTHREF). Set SOC.CFGAIO7.OPT7 to select the comparator reference. To select the VTHREF comparator threshold use SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V -68- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 69: Aio7 Special Mode

    Set SOC.CFGAIO7.MODE7 = 11b to use AIO<9:7> in special mode. In special mode the AIO7 special mode comparator is enabled. -69- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 70 IRQ2 to the MCU. The interrupt status can be monitored by reading SOC.SIGINTEN.AIO7INT and cleared by writing SOC.SIGINTEN.AIO7INTF to 1b. -70- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 71 IRQ2 interrupt signal. To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -71- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 72: Aio8

    ® Power Application Controller 10.15 AIO8 AIO8 may be configured as a digital input, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -72- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 73: System Block Diagram

    CFGAIO9.MODE9[1] CFGAIO9.MUX9[0] CFGAIO8.OPT8[0] CFGAIO8.OPT8[1] CMP Polarity AB<3:1> IRQ2/POS ABUS CFGAIO8.POL8 AIO7 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN8 SIGINTF.AIO8INT SPECCFG2.SMUXAIO8 SIGINTEN.AIO8REINTEN BLANKING.BLANKTIME SIGINTEN.AIO8FEINTEN BLANKING.BLANKMODE SPECCFG0.HYSMODE SPECCFG1.AIO8HYS CFGAIO8.MODE8 EMUX IRQ2 -73- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 74: Aio8 Digital I/O Mode

    (VTHREF). Set SOC.CFGAIO8.OPT8 to select the comparator reference. To select the VTHREF comparator threshold use SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V -74- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 75: Aio8 Special Mode

    Set SOC.CFGAIO7.MODE7 = 11b to use AIO<9:7> in special mode. In special mode the AIO8 special mode comparator is enabled. -75- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 76 IRQ2 to the MCU. The interrupt status can be monitored by reading SOC.SIGINTEN.AIO8INT and cleared by writing SOC.SIGINTEN.AIO8INTF to 1b. -76- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 77 IRQ2 interrupt signal. To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -77- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 78: Aio9

    ® Power Application Controller 10.16 AIO9 AIO9 may be configured as a digital input, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -78- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 79: System Block Diagram

    CFGAIO9.MODE9[1] CFGAIO9.MUX9[0] CFGAIO8.OPT8[0] CFGAIO8.OPT8[1] CMP Polarity AB<3:1> IRQ2/POS ABUS CFGAIO9.POL9 AIO8 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN9 SIGINTF.AIO9INT SPECCFG2.SMUXAIO9 BLANKING.BLANKTIME SIGINTEN.AIO9REINTEN SIGINTEN.AIO9FEINTEN BLANKING.BLANKMODE SPECCFG0.HYSMODE SPECCFG1.AIO9HYS EMUX IRQ2 IRQ2 -79- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 80: Aio9 Digital I/O Mode

    (VTHREF). Set SOC.CFGAIO9.OPT9 to select the comparator reference. To select the VTHREF comparator threshold use SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V -80- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 81 IRQ2 to the MCU. The interrupt status can be monitored by reading SOC.SIGINTEN.AIO9INT and cleared by writing SOC.SIGINTEN.AIO9INTF to 1b. -81- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 82: Aio9 Special Mode

    (asymmetric and bi-directional). To set the comparator hysteresis scale for AIO9, set SOC.SPECCFG0.HYSMODE and to set the hysteresis level set SOC.SPECCFG1.AIO9HYS. The output polarity of the comparator may be selected by using SOC.CFGAIO9.POL9 (0b: active-high; 1b: active-low). -82- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 83 IRQ2 interrupt signal. To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -83- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 84: Register Summary

    0x22 SOC.SPECCFG0 AIO7 Hysteresis Configuration 0x00 0x23 SOC.SPECCFG1 AIO8/AIO9 Hysteresis Configuration 0x00 0x24 SOC.SPECCFG2 AIO7/AIO8 Comparator Input MUX Configuration 0x00 0x25 SOC.SPECCFG3 AIO9 Comparator Input MUX Configuration 0x00 -84- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 85: Register Detail

    LP10EN: LP10 Comparator option: MUX0 011b: DB3 100b: DB4 00b: disabled 101b: DB5 01b: 1µs blanking time 110b: DB6 10b: 2µs blanking time 111b: DB7 11b: 4µs blanking time -85- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 86: Soc.cfgaio1

    HP10EN: HP10 Comparator setting: 010b: DB2 MUX1 011b: DB3 00b: disabled 100b: DB4 01b: 1µs blanking time 101b: DB5 10b: 2µs blanking time 110b: DB6 11b: 4µs blanking time 111b: DB7 -86- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 87: Soc.cfgaio2

    LP32EN: LP32 Comparator setting: 010b: DB2 MUX2 011b: DB3 00b: disabled 100b: DB4 01b: 1µs blanking time 101b: DB5 10b: 2µs blanking time 110b: DB6 11b: 4µs blanking time 111b: DB7 -87- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 88: Soc.cfgaio3

    HP32EN: HP32 Comparator setting: 010b: DB2 MUX3 011b: DB3 00b: disabled 100b: DB4 01b: 1µs blanking time 101b: DB5 10b: 2µs blanking time 110b: DB6 11b: 4µs blanking time 111b: DB7 -88- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 89: Soc.cfgaio4

    LP54EN: LP54 Comparator setting: 010b: DB2 MUX4 011b: DB3 00b: disabled 100b: DB4 01b: 1µs blanking time 101b: DB5 10b: 2µs blanking time 110b: DB6 11b: 4µs blanking time 111b: DB7 -89- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 90: Soc.cfgaio5

    HP54EN: HP54 Comparator setting: 010b: DB2 MUX5 011b: DB3 00b: disabled 100b: DB4 01b: 1µs blanking time 101b: DB5 10b: 2µs blanking time 110b: DB6 11b: 4µs blanking time 111b: DB7 -90- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 91: Soc.cfgaio6

    100b: AB4 100b: DB4 101b: DB5 101b: AB5 101b: AB5 101b: DB5 110b: DB6 110b: AB6 110b: AB6 110b: DB6 111b: DB7 111b: AB7 111b: AB7 111b: DB7 -91- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 92: Soc.cfgaio7

    011b: AB3 011b: DB3 100b: DB4 100b: AB4 100b: DB4 101b: DB5 101b: AB5 101b: DB5 110b: DB6 110b: AB6 110b: DB6 111b: DB7 111b: AB7 111b: DB7 -92- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 93: Soc.cfgaio8

    011b: AB3 011b: DB3 100b: DB4 100b: AB4 100b: DB4 101b: DB5 101b: AB5 101b: DB5 110b: DB6 110b: AB6 110b: DB6 111b: DB7 111b: AB7 111b: DB7 -93- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 94: Soc.cfgaio9

    101b: DB5 101b: DB5 101b: AB5 110b: DB6 110b: DB6 MUX9[0]: 1 = Switch MUXed raw comparator 110b: AB6 111b: DB7 111b: DB7 output to DB6. 111b: AB7 -94- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 95: Soc.sigset

    0b: LPDAC output not connected to AB3 1b: LPDAC output connected to AB3 Connect HPDAC output to AB2: HPDACAB2 0b: HPDAC output not connected to AB2 1b: HPDAC output connected to AB2 -95- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 96: Soc.hpdach

    LPDAC MSB setting bits 9:2. 10.18.15 SOC.LPDACL Register 10-15 SOC.LPDAC1 (LPDAC Low Setting, 14h) NAME ACCESS RESET DESCRIPTION Reserved, write to 0x0. LPDAC LPDAC LSB Setting bits 1:0. -96- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 97: Soc.shcfg1

    Amplifier 32 output to ADCIN: DAO32SH 0b: Disabled 1b: Enabled Enable sample and hold circuit to synchronize the Differential Amplifier 10 output to ADCIN: DAO10SH 0b: Disabled 1b: Enabled -97- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 98: Soc.shcfg2

    0100b: AB2 0101b: AB3 0110b: AB4 MUXA 0111b: AB5 1000b: AB6 1001b: AB7 1010b: AB8 1011b: AB9 1100b: VPTAT 1101b: AB11 1110b: VP / 10 1111b: VREF / 2 -98- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 99: Soc.protinten

    Reserved, write to 0. LPROT54 Interrupt enable: LP54INTEN 0b: Not enabled 1b: Enabled LPROT32 Interrupt enable: LP32INTEN 0b: Not enabled 1b: Enabled LPROT10 Interrupt enable: LP10INTEN 0b: Not enabled 1b: Enabled -99- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 100: Soc.protstat

    1b: Interrupt, write 1b to clear LPROT32 Interrupt: LP32INT 0b: No interrupt 1b: Interrupt, write 1b to clear LPROT10 Interrupt: LP10INT 0b: No interrupt 1b: Interrupt, write 1b to clear -100- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 101: Soc.doutsig0

    ACCESS RESET DESCRIPTION 000b Reserved, write to 0. DOUT9 Data output to AIO9. DOUT8 Data output to AIO8. DOUT7 Data output to AIO7. DOUT6 Data output to AIO6. -101- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 102: Soc.dinsig0

    Driver fault input. Set to 1b when driver short is detected. DIN9 Data input from AIO9. DIN8 Data input from AIO8. DIN7 Data input from AIO7. DIN6 Data input from AIO6. -102- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 103: Soc.cfgio1

    Enable AIO6 comparator output to disable gate driver on OC EN_AIO6_OCP event. Switch VREF signal to AB5 so that it can be buffered out on VREFBP AIO6. 000b Reserved, write as 0. -103- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 104: Soc.siginten

    0b: disabled 1b: enabled AIO7 digital input falling edge interrupt enable. AIO7FEINTEN 0b: disabled 1b: enabled AIO6 digital input falling edge interrupt enable. AIO6FEINTEN 0b: disabled 1b: enabled -104- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 105: Soc.sigintf

    AIO7 Interrupt: AIO7INT 0b: No Interrupt 1b: Interrupt, IRQ2 asserted. Write 1b to clear. AIO6 Interrupt: AIO6INT 0b: No Interrupt 1b: Interrupt, IRQ2 asserted. Write 1b to clear. -105- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 106: Soc.blanking

    1110b: 5500ns 1111b: 6000ns Reserved, write as 0. BEMF Comparator Blanking Mode: 00b: Disabled BLANKMODE 01b: Leading edge blanking 10b: Trailing edge blanking 11b: Leading and trailing edge blanking -106- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 107: Soc.speccfg0

    1100b: Rising = 80mV, Falling = 0mV 1101b: Rising = 80mV, Falling = 20mV 1110b: Rising = 80mV, Falling = 40mV 1111b: Rising = 80mV, Falling = 80mV -107- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 108: Soc.speccfg1

    1100b: Rising = 20mV, Falling = 0mV 1101b: Rising = 20mV, Falling = 5mV 1110b: Rising = 20mV, Falling = 10mV 1111b: Rising = 20mV, Falling = 20mV -108- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 109: Soc.speccfg2

    000b: VTHREF 001b: AB1 (virtual center-tap) 010b: AB2 SMUXAIO8 000b 011b: AB3 100b: AIO7 (phase to phase compare) 101b: AIO9 (phase to phase compare) 110b: RFU 111b: RFU -109- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 110: Soc.speccfg3

    001b: AB1 (virtual center-tap) 010b: AB2 SMUXAIO9 000b 011b: AB3 100b: AIO7 (phase to phase compare) 101b: AIO8 (phase to phase compare) 110b: RFU 111b: RFU 000b Reserved, write to 0x0. -110- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 111: Application Specific Power Driver

    3 high-side gate drivers with 250mA sink and 500mA source current ▪ 3 low-side gate drivers with 1A sink and 1A source current ▪ Fast fault protection ▪ Cycle-by-cycle current limit function -111- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 112: System Block Diagram

    Figure 11-1 ASPD System Block Diagram APPLICATION SPECIFIC POWER DRIVERS HIGH-SIDE GATE DRIVERS DXBx LEVEL PRE- DXHx SHIFT DRIVER DXSx FAULT PROTECT & CURRENT LIMIT LOW-SIDE GATE DRIVERS PRE- DRLx DRIVER ENDRV -112- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 113: Functional Description

    The input to the 3 high-side gate drivers are shown below: • DXH0: PC4 (PWMB4) • DXH1: PC5 (PWMB5) • DXH2: PC6 (PWMB6) -113- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 114: Low-Side Gate Drivers

    PWM timer peripheral and can configure the dead-time between complementary high-side/low-side pairs. The input to the 3 low-side gate drivers are shown below: • DRL0: PB0 (PWMB0) • DRL1: PB1 (PWMB1) • DRL2: PB2 (PWMB2) -114- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 115 Once the gate drivers have been disabled, the MCU must reset the ASPD by setting SOC.ENDRV.ENDRV to 0b, then back to 1b in order to re-enable the ASPD. -115- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 116: Figure 11-3 Cycle By Cycle Current Limit

    During operation, if the PWMCBC signal is high, then the output to the configured gate drivers is temporarily disabled, until the PWMCBC becomes available again. The following shows which drivers are disabled during this condition: • PWMCBC = high: -116- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 117 ◦ If SOC.CFGDRV2.LPCBCLS = 1b and SOC.CFGDRV2.DRV41DIS = 1b, disable DRL1 • PWMCBC = high: ◦ If SOC.CFGDRV2.LPCBCHS = 1b and SOC.CFGDRV2.DRV30DIS = 1b, disable DXH0 ◦ If SOC.CFGDRV2.LPCBCLS = 1b and SOC.CFGDRV2.DRV30DIS = 1b, disable DRL0 -117- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 118 VP crosses V and k . When VP is falling, the VP UVLO threshold is set UVLOR;VP POKR;VP when VP crosses V and k UVLOF;VP POKF;VP -118- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 119: Table 11-1 Aspd Register Summary

    SOC.CFGDRV2 Driver Configuration 2 SOC.CFGDRV3 Driver Configuration 3 SOC.STATDRV Driver Status SOC.CFGDRV4 Driver Configuration 4 SOC.DRV_FLT Driver Fault Flag SOC.ENDRV Driver Manager Enable SOC.WDTPASS SOC Watchdog Timer Password -119- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 120: Register 11-1 Soc.cfgdrv1 (Driver Configuration 1, 27H)

    High side PR protection enable: HSPREN 0b: PR disabled 1b: PR enabled Low side PR protection enable: LSPREN 0b: PR disabled 1b: PR enabled Reserved, write as 0x0. -120- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 121: Register 11-2 Soc.cfgdrv2 (Driver Configuration 2, 28H)

    0b: Do not disable 1b: Disable when commanded Control signal for high-side gate drivers disable. Used for PWM pulse cycle-by-cycle current limit: LPCBCHS 0b: Do not disable 1b: Disable when commanded -121- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 122: Register 11-3 Soc.cfgdrv3 (Driver Configuration 3, 29H)

    HP10CBCM 0b: enabled 1b: not enabled Enable signal for LPROT10 for PWM pulse cycle-by-cycle current limit: LP10CBCM 0b: enabled 1b: not enabled Reserved, write as 0. -122- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 123: Register 11-4 Soc.statdrv (Driver Status, 2Ah)

    1b: Driver disable event occurred Latched status of DRV10DIS signal. To clear, write this bit to a 1b: DRV10DIS 0b: No driver disable event 1b: Driver disable event occurred -123- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 124: Register 11-5 Soc.cfgdrv4 (Driver Configuration 4, 7Bh)

    Register 11-7 SOC.ENDRV (Driver Manager Enable, 7Dh) NAME ACCESS RESET DESCRIPTION Reserved, write as 0. Driver Fault Detection Enabled: DRVFLTEN 0b: Disabled 1b: Enabled Driver Manager Enable: ENDRV 0b: Disable 1b: Enable -124- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

  • Page 125: Register 11-8 Soc.wdtpass (Wdt Password, 7Eh)

    ® Power Application Controller 11.13.8 SOC.WDTPASS Register 11-8 SOC.WDTPASS (WDT Password, 7Eh) NAME ACCESS RESET DESCRIPTION WDTPASS To reset the SOC Watchdog Timer, write this field to ACh. -125- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...
  • Page 126 ARM Limited. All referenced brands and trademarks are the property of their respective owners. For more information on this and other products, contact sales@active-semi.com or visit www.active-semi.com. -126- © Copyright 2020 Qorvo, Inc. Rev 2.2 – Nov 25, 2020...

Table of Contents