Qorvo PAC5526 Manuals

Manuals and User Guides for Qorvo PAC5526. We have 1 Qorvo PAC5526 manual available for free PDF download: User Manual

Qorvo PAC5526 User Manual (129 pages)

Power Application Controller

Brand: Qorvo | Category: Controller | Size: 1.42 MB

Table of Contents
2
Overview
12
Style and Formatting Conventions
13
Number Representation
13
Formatting Styles
13
Architectural Block Diagram
14
Figure 3-1 PAC5526 Architectural Block Diagram
14
Analog Register Access
15
Overview
15
Functional Description
15
Figure 4-1 PAC5526 Register Access
15
USART Configuration
16
Protocol
16
Write Register Example
16
Figure 4-2 Analog Peripheral Register Write Timing
17
Read Register Example
18
Figure 4-3 Analog Peripheral Register Read Timing
18
Pac5526 Io
19
Overview
19
Figure 5-1 GPIO and DPM Block Diagram
19
ADC Channels
20
Table 5-1 PAC5526 ADC Input Pins
20
Digital Peripheral Pins
21
Table 5-2 PAC5526 Digital Peripheral Pins
21
Analog Interrupts
22
PAC5526 ADC Muxes
23
System Block Diagram
23
Figure 6-1 PAC5526 ADC MUX Inputs
23
Adc Mux
24
Table 6-1 PAC5526 ADC MUX Channels
24
Afe Mux
25
Table 6-2 PAC5526 ADC MUX Channels
26
Pwrmon Mux
27
Table 6-3 PAC5526 ADC MUX Channels
27
Emux
28
Figure 7-1 EMUX Timing Diagram
29
Power Manager
30
Overview
30
Features
30
System Block Diagram
31
Functional Description
31
VP Low Warning
31
Figure 8-1 Power Manager System Block Diagram
31
Power Manager Faults
32
Temperature Warnings and Faults
32
Table 8-1 Power Manager Fault Handling
32
Register Summary
34
Table 8-2 Power Manager Register Summary
34
Register Detail
35
Soc.fault
35
Soc.status
35
Register 8-1 SOC.FAULT (Fault Condition, 00H)
35
Register 8-2 SOC.STATUS (System Status, 01H)
35
Soc.misc
37
Register 8-3 SOC.MISC (SOC Miscellaneous Configuration, 02H)
37
Soc.pwrctl
38
Register 8-4 SOC.PWRCTL (Power Control, 03H)
38
Soc.faultinten
39
Register 8-5 SOC.FAULTINTEN (Fault Interrupt Enable, 04H)
39
Soc.watchdog
40
Register 8-6 SOC.WATCHDOG (SOC Watchdog Configuration, 05H)
40
Soc.sysconf
41
Register 8-7 SOC.SYSCONF (System Configuration, 2Bh)
41
Configurable Analog Front-End
42
Overview
42
Features
42
System Block Diagram
43
Figure 9-1 CAFE System Block Diagram
43
Enabling the CAFE
44
Entering Hibernate Mode
44
Hibernate Wake-Up Using Wake-Up Timer
44
Hibernate Wake-Up Using Push-Button
44
Table 9-1 Hibernate Wake-Up Timer Options
44
DAC Output
45
VREF Output
45
Hard Reset
45
General-Purpose Register
45
Aio10
46
System Block Diagram
46
Figure 9-2 AIO10 Block Diagram
46
AIO1, AIO0 Digital I/O Mode
47
AIO1, AIO0 Differential Amplifier Mode
47
AIO1, AIO0 ADC Sampling
47
AIO1, AIO0 Protection
48
Aio32
50
System Block Diagram
50
Figure 9-3 AIO32 Block Diagram
50
AIO3, AIO2 Digital I/O Mode
51
AIO3, AIO2 Differential Amplifier Mode
51
AIO3, AIO2 ADC Sampling
51
AIO3, AIO2 Protection
52
AIO2/AIO7 Buffer
53
Table 9-2 AIO2/AIO7 Buffer Input Select
53
Aio54
54
System Block Diagram
54
Figure 9-4 AIO54 Block Diagram
54
AIO5, AIO4 Digital I/O Mode
55
AIO4, AIO5 Differential Amplifier Mode
55
AIO5, AIO4 ADC Sampling
55
AIO5, AIO4 Protection
56
Aio6
58
System Block Diagram
59
Figure 9-5 AIO6 System Block Diagram
59
AIO6 Digital I/O Mode
60
AIO6 Amplifier Mode
60
AIO6 Comparator Mode
60
AIO6 Special Mode
61
Aio7
62
System Block Diagram
63
Figure 9-6 AIO7 System Block Diagram
63
AIO7 Digital I/O Mode
64
AIO7 Amplifier Mode
64
AIO7 Comparator Mode
64
AIO7 Special Mode
65
AIO2/AIO7 Buffer
67
Table 9-3 AIO2/AIO7 Buffer Input Select
67
Aio8
68
System Block Diagram
69
Figure 9-7 AIO8 System Block Diagram
69
AIO8 Digital I/O Mode
70
AIO8 Amplifier Mode
70
AIO8 Comparator Mode
70
AIO8 Special Mode
71
Aio9
73
System Block Diagram
74
Figure 9-8 AIO9 System Block Diagram
74
AIO9 Digital I/O Mode
75
AIO9 Amplifier Mode
75
AIO9 Comparator Mode
75
AIO9 Special Mode
76
Register Summary
78
Table 9-4 CAFE Register Summary
78
Register Detail
80
Soc.cfgaio0
80
Register 9-1 SOC.CFGAIO0 (AIO0 Configuration, 06H)
80
Soc.cfgaio1
81
Register 9-2 SOC.CFGAIO1 (AIO1 Configuration, 07H)
81
Soc.cfgaio2
82
Register 9-3 SOC.CFGAIO2 (AIO2 Configuration, 08H)
82
Soc.cfgaio3
83
Register 9-4 SOC.CFGAIO3 (AIO3 Configuration, 09H)
83
Soc.cfgaio4
84
Register 9-5 SOC.CFGAIO4 (AIO4 Configuration, 0Ah)
84
Soc.cfgaio5
85
Register 9-6 SOC.CFGAIO5 (AIO5 Configuration, 0Bh)
85
Soc.cfgaio6
86
Register 9-7 SOC.CFGAIO6 (AIO6 Configuration, 0Ch)
86
Soc.cfgaio7
87
Register 9-8 SOC.CFGAIO7 (AIO7 Configuration, 0Dh)
87
Soc.cfgaio8
88
Register 9-9 SOC.CFGAIO8 (AIO8 Configuration, 0Eh)
88
Soc.cfgaio9
89
Register 9-10 SOC.CFGAIO9 (AIO9 Configuration, 0Fh)
89
Soc.sigset
90
Register 9-11 SOC.SIGSET (Signal Manager Configuration, 10H)
90
Soc.hpdach
91
Soc.hpdacl
91
Soc.lpdach
91
Soc.lpdacl
91
Register 9-12 SOC.HPDACH (HPDAC High Setting, 11H)
91
Register 9-13 SOC.HPDACL (HPDAC Low Setting, 12H)
91
Register 9-14 SOC.LPDACH (LPDAC High Setting, 13H)
91
Register 9-15 SOC.LPDAC1 (LPDAC Low Setting, 14H)
91
Soc.shcfg1
92
Register 9-16 SOC.SHCFG1 (Sample and Hold Configuration, 15H)
92
Soc.shcfg2
93
Register 9-17 SOC.SHCFG2 (Sample and Hold Configuration 2, 16H)
93
Soc.protinten
94
Register 9-18 SOC.PROTINTEN (Protection Interrupt Enable, 17H)
94
Soc.protstat
95
Register 9-19 SOC.PROTSTAT (Protection Interrupt Status, 18H)
95
Soc.doutsig0
96
Register 9-20 SOC.DOUTSIG0 (Digital Output 0, 19H)
96
Soc.doutsig1
97
Register 9-21 SOC.DOUTSIG1 (Digital Output 1,1Ah)
97
Soc.dinsig0
98
Soc.dinsig1
98
Register 9-22 SOC.DINSIG0 (Digital Input 0, 1Bh)
98
Register 9-23 SOC.DINSIG1 (Digital Input 1, 1Ch)
98
Soc.cfgio1
99
Register 9-24 SOC.CFGIO1 (AIO10-AIO13 Configuration 1, 1Dh)
99
Soc.siginten
100
Register 9-25 SOC.SIGINTEN (AIO Interrupt Enable, 1Fh)
100
Soc.sigintf
101
Register 9-26 SOC.SIGINTF (AIO Interrupt Flag, 20H)
101
Soc.blanking
102
Register 9-27 SOC.BLANKING (Comparator Blanking Configuration, 21H)
102
Soc.speccfg0
103
Register 9-28 SOC.SPECCFG0 (AIO7 Comparator Hysteresis Configuration, 22H)
103
Soc.speccfg1
104
Register 9-29 SOC.SPECCFG1 (AIO8/9 Comparator Hysteresis Configuration, 23H)
104
Soc.speccfg2
106
Soc.speccfg3
106
Register 9-30 SOC.SPECCFG2 (AIO7/8 Comparator MUX Input Configuration, 24H)
106
Register 9-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25H)
106
Soc.gp0
107
Register 9-32 SOC.GP0 (General-Purpose Register Space, 26H)
107
Application Specific Power Driver
108
Features
108
System Block Diagram
109
Figure 10-1 ASPD System Block Diagram
109
Functional Description
110
High-Side Gate Drivers
110
Figure 10-2 High-Side Gate Driver Block Diagram
110
Low-Side Gate Drivers
111
Figure 10-3 Low-Side Gate Driver Block Diagram
111
Enabling the ASPD
112
Gate Driver Safe State
112
Driver Protection
112
Cycle by Cycle Current Limit
113
Figure 10-4 Cycle by Cycle Current Limit
113
Gate Driver Short Protection
115
VP UVLO Configuration
115
Break-Before-Make Configuration
115
Gate Driver Programmable Current
116
Figure 10-5 High-Side Gate Driver Waveforms
116
Figure 10-6 Low-Side Gate Driver Waveforms
117
Table 10-1 ASPD Controlled-Current Time Configuration
118
Table 10-2 ASPD Controlled-Current Time Configuration
119
Register Summary
120
Table 10-3 ASPD Register Summary
120
Register Detail
121
Soc.cfgdrv1
121
Register 10-1 SOC.CFGDRV1 (Driver Configuration 1, 27H)
121
Soc.cfgdrv2
122
Register 10-2 SOC.CFGDRV2 (Driver Configuration 2, 28H)
122
Soc.cfgdrv3
123
Register 10-3 SOC.CFGDRV3 (Driver Configuration 3, 29H)
123
Soc.statdrv
124
Register 10-4 SOC.STATDRV (Driver Status, 2Ah)
124
Soc.drvilimls
125
Register 10-5 SOC.DRVILIMLS (Low-Side Driver Current Limit Configuration, 79H)
125
Soc.drvilimhs
126
Register 10-6 SOC.DRVILIMHS (High-Side Driver Current Limit Configuration, 7Ah)
126
Soc.cfgdrv4
127
Soc.drv_Flt
127
Register 10-7 SOC.CFGDRV4 (Driver Configuration 4, 7Bh)
127
Register 10-8 SOC.DRV_FLT (Driver Fault Flat, 7Ch)
127
Soc.endrv
128
Soc.wdtpass
128
Register 10-9 SOC.ENDRV (Driver Manager Enable, 7Dh)
128
Register 10-10 SOC.WDTPASS (WDT Password, 7Eh)
128
Legal Information
129

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Qorvo PAC5526 User Manual (129 pages)

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