Page 1 ® Power Application Controller PAC5526 Device User Guide ® Power Application Controller Multi-Mode Power Manager Configurable Analog Front End Application Specific Power Drivers ® ® Cortex -M4F Controller Core Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 2: Table Of Contents
Read Register Example ....................18 PAC5526 IO ........................19 Overview ........................19 ADC Channels ......................20 Digital Peripheral Pins ....................21 Analog Interrupts ......................22 PAC5526 ADC MUXes ......................23 System Block Diagram ....................23 ADC MUX ........................24 AFE MUX ........................25 PWRMON MUX ......................27 EMUX ..........................28 POWER MANAGER ......................30 Overview ........................30...
Page 3 AIO1, AIO0 Differential Amplifier Mode ..............47 9.12.4 AIO1, AIO0 ADC Sampling ..................47 9.12.5 AIO1, AIO0 Protection ..................48 9.13 AIO32 .........................50 9.13.1 System Block Diagram ..................50 9.13.2 AIO3, AIO2 Digital I/O Mode ................51 Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 4 9.17.3 AIO8 Amplifier Mode ....................70 9.17.4 AIO8 Comparator Mode ..................70 9.17.5 AIO8 Special Mode ....................71 9.18 AIO9 ...........................73 9.18.1 System Block Diagram ..................74 9.18.2 AIO9 Digital I/O Mode ..................75 Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 5 SOC.PROTSTAT .....................95 9.20.20 SOC.DOUTSIG0 ....................96 9.20.21 SOC.DOUTSIG1 ....................97 9.20.22 SOC.DINSIG0 ....................98 9.20.23 SOC.DINSIG1 ....................98 9.20.24 SOC.CFGIO1 ....................99 9.20.25 SOC.SIGINTEN ..................... 100 9.20.26 SOC.SIGINTF ....................101 9.20.27 SOC.BLANKING .................... 102 Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 6 SOC.STATDRV ....................124 10.15.5 SOC.DRVILIMLS.................... 125 10.15.6 SOC.DRVILIMHS ................... 126 10.15.7 SOC.CFGDRV4 ..................... 127 10.15.8 SOC.DRV_FLT ....................127 10.15.9 SOC.ENDRV ....................128 10.15.10 SOC.WDTPASS ..................... 128 LEGAL INFORMATION ....................129 Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 8 ® Power Application Controller LIST OF FIGURES Figure 3-1 PAC5526 Architectural Block Diagram ..............14 Figure 4-1 PAC5526 Register Access ..................15 Figure 4-2 Analog Peripheral Register Write Timing ..............17 Figure 4-3 Analog Peripheral Register Read Timing ..............18 Figure 5-1 GPIO and DPM Block Diagram ................19 Figure 6-1 PAC5526 ADC MUX inputs ..................23...
Page 9 ® Power Application Controller LIST OF TABLES Table 5-1 PAC5526 ADC Input Pins ..................20 Table 5-2 PAC5526 Digital Peripheral Pins ................21 Table 6-1 PAC5526 ADC MUX channels ..................24 Table 6-2 PAC5526 ADC MUX channels ..................26 Table 6-3 PAC5526 ADC MUX channels ..................27 Table 8-1 Power Manager Fault Handling .................32...
Page 10 Register 9-31 SOC.SPECCFG3 (AIO9 Comparator MUX Input Configuration, 25h) ....106 Register 9-32 SOC.GP0 (General-Purpose Register Space, 26h)........... 107 Register 10-1 SOC.CFGDRV1 (Driver Configuration 1, 27h) ..........121 -10- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 11 Register 10-7 SOC.CFGDRV4 (Driver Configuration 4, 7Bh) ..........127 Register 10-8 SOC.DRV_FLT (Driver Fault Flat, 7Ch) ............127 Register 10-9 SOC.ENDRV (Driver Manager Enable, 7Dh) ............ 128 Register 10-10 SOC.WDTPASS (WDT Password, 7Eh) ............128 -11- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 12: Overview
® Power Application Controller OVERVIEW This document is the PAC5526 Device User Guide. It details the operation of the analog peripherals in the PAC5526. For detailed information on the MCU and Digital Peripherals in the PAC5526, see the PAC55XX Family User Guide.
Page 13: Style And Formatting Conventions
CPU Mnemonic uses monospaced text. CPU Mnemonic {Rd, }, Rn, Rm Operands use monospaced italic text. Operands b loopA Code examples Code examples use monospaced text. -13- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 14: Architectural Block Diagram
® Power Application Controller ARCHITECTURAL BLOCK DIAGRAM For Below is an architecture block diagram of the PAC5526 device. Figure 3-1 PAC5526 Architectural Block Diagram PAC5526 POWER Power Application Controller MANAGER PX.Y HVCP DEBUG/ 128kB FLASH MVBB CORTEX-M4F 3 x 1kB FLASH...
Page 15: Analog Register Access
Power Application Controller ANALOG REGISTER ACCESS Overview All analog registers in the PAC5526 are accessible through a SOC bus in the device. Unlike registers in the MCU (SRAM and digital peripheral registers), these analog registers are not memory mapped. The block diagram below shows the different system busses that the MCU uses to access the different system registers.
Page 16: Usart Configuration
Write SSPADAT with the value 57h (2Bh << 1 | 1b for write transaction) ▪ Write SSPADAT with the value 28h The timing diagram from a write operation is shown below. -16- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 17: Figure 4-2 Analog Peripheral Register Write Timing
® Power Application Controller Figure 4-2 Analog Peripheral Register Write Timing -17- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 18: Read Register Example
Figure 4-3 Analog Peripheral Register Read Timing For more information on how to configure the DPM to support the USART A peripheral for communicating with the Analog Registers, see the PAC55XX Family User Guide. -18- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 19: Pac5526 Io
ADC input. For information on how to configure the IO for each of these situations, see the PAC55XX Family User Guide. The PAC5526 has the following IO pins available for application use: ▪ PA[7:0] – Reserved for MMPM, ASPD, CAFE ▪...
Page 20: Adc Channels
® Power Application Controller ADC Channels The ADC channels that are available on the PAC5526 are shown in the table below. Table 5-1 PAC5526 ADC Input Pins ADC Channel IO PIN ADC0 ADC1 ADC2 ADC4 ADC5 ADC6 ADC7 Available for sampling channels in the CAFE only -20- Copyright 2020 ©...
Page 21: Digital Peripheral Pins
® Power Application Controller Digital Peripheral Pins The digital peripheral functions that are available in the PAC5526 are shown below. Table 5-2 PAC5526 Digital Peripheral Pins GPIOxMUXS.Py PORT 000b 001b 010b 011b 100b 101b 110b 111b GPIOA0 GPIOA1 EMUXD GPIOA2...
Page 22: Analog Interrupts
I2CSDA USDMISO CANTXD TDQEPPHB For more information on how to configure the DPM for the PAC5526, see the PAC55XX Family User Guide. Analog Interrupts The Analog Front-end may interrupt the MCU during operation when certain system conditions occur. There are two analog interrupts available: •...
Page 23: Pac5526 Adc Muxes
® Power Application Controller PAC5526 ADC MUXes The PAC5526 allows the user to internally monitor the various internal and external analog channels through a series of MUXes on the MCU and AFE. System Block Diagram The various MUXes that are used for signal sampling are shown in the diagram below.
Page 24: Adc Mux
ADC and ADC MUX are done automatically in hardware according the DTSE and ADC configuration. In the PAC5526, there are 4 external pins and one internal ADC channel that may be configured for ADC analog input that are shown in the table below.
Page 25: Afe Mux
(enabled). The AFE MUX channel may be selected from the EMUX data sent from the DTSE. The channels available on the AFE MUX are shown in the table below. -25- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 26: Table 6-2 Pac5526 Adc Mux Channels
® Power Application Controller Table 6-2 PAC5526 ADC MUX channels AFE MUX Channel Value Description DAO10 0000b Output of Differential Amplifier for AIO10. DAO32 0001b Output of Differential Amplifier for AIO32. DAO54 0010b Output of Differential Amplifier for AIO54. 0011b Analog bus AB1.
Page 27: Pwrmon Mux
The PWRMON MUX output is on the analog bus channel AB11, which is directly connected to the AFE MUX. The channels available on the PWRMON MUX are shown in the table below. Table 6-3 PAC5526 ADC MUX channels Channel SOC.PWRCTL.PWRMON...
Page 28: Emux
0110b: AB4 MUXA 0111b: AB5 1000b: AB6 1001b: AB7 1010b: AB8 1011b: AB9 1100b: AB10 (VPTAT) 1101b: AB11 (PWRMON) 1110b: AB12 (VP / 10) 1111b: AB13 (VM / 20) -28- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 29: Figure 7-1 Emux Timing Diagram
3:0 of the EMUX packet. Figure 7-1 EMUX Timing Diagram EMUXC EMUXD HDL2 HDL1 HDL0 MUX3 MUX2 MUX1 MUX0 POS S/H DAOxy S/H MUXA -29- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 30: Power Manager
5 additional Linear regulators with power and hibernate management ▪ High-accuracy voltage reference for ADC and comparators ▪ Power and temperature monitor, warning, fault detection ▪ Extremely low hibernate mode I of 10µA -30- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 31: System Block Diagram
SOC.STATUS.VPLOW is set to 1b • SOC.STATUS.VPLOW_LATCH is set to 1b • If the SOC.FAULTEN.nVPFLT bit is set to 1b, the IRQ1 interrupt to the MCU is asserted -31- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 32: Power Manager Faults
To reset the fault condition, the corresponding fault bit(s) should be written to a 1b and then the power supplies will be re-started according to the power supply sequence. Temperature Warnings and Faults The PAC5526 monitors the device temperature for two different thresholds: • Temperature Warning •...
Page 33 When the die temperature exceeds the fault threshold of 165°C, the SOC.FAULT.TMPFAULT bit is set to 1b. When this fault occurs, the PAC5526 is forced into hibernate mode and will stay in hibernate mode until the push-button or wake-up timer (if configured) is received.
Page 34: Register Summary
Hardware status condition register SOC.MISC Miscellaneous features register SOC.PWRCTL Power Manager control register SOC.FAULTEN Power Manager fault mask register SOC.WATCHDOG SOC Watchdog configuration register SOC.SYSCONF Power Manager system configuration register -34- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 35: Register Detail
1b: VCC33 fault VCORE fault. Set on fault, and cleared when written to 1b. VCOREFLT 0b: No VCORE fault 1b: VCORE fault 8.9.2 SOC.STATUS Register 8-2 SOC.STATUS (System Status, 01h) -35- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 37: Soc.misc
Drive high externally to wake-up. Signal Manager Enable. This bit is automatically cleared when the reset signal to the MCU is asserted. SMEN 0b: Not enabled 1b: Enabled -37- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 38: Soc.pwrctl
100b: VSYS x 4/10 101b: VREF/2 110b: VPTAT 111b: (VCP-VM) x 5/10 Wake-up Timer: 000b: infinite 001b: 8ms 010b: 16ms WUTIMER 011b: 32ms 100b: 64ms 101b: 1s 110b: 2s 111b: 4s -38- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 39: Soc.faultinten
0b: Not enabled 1b: Enabled (asserts IRQ1) VP Low Interrupt Enabled. VPINT 0b: Not enabled 1b: Enabled (asserts IRQ1) This byte is unlocked for writing when UNLOCK = 1b. -39- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 40: Soc.watchdog
Watchdog Timer Enable. Cleared during hard reset. WDTEN 0b: disabled 1b: enabled Watch-dog Timer. 000b: 62.5ms 001b: 125ms 010b: 250ms 011b: 500ms 100b: 1s 101b: 2s 110b: 4s 111b: 8s -40- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 41: Soc.sysconf
VP Output Voltage Setting. VPSET 0b: 10V 1b: 12V (default) MVBB Inductor Current Limit Range: MVBB_ILIM 0b: 440mA-540mA (default) 1b: 600mA-750mA Charge Pump Enable: CP_EN 0b: Disabled 1b: Enabled -41- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 42: Configurable Analog Front-End
CONFIGURABLE ANALOG FRONT-END Overview The PAC5526 includes a Configurable Analog Front End accessible through 8 analog and I/O pins. These pins can be configured to form flexible interconnected circuitry made up of 3 differential programmable gain amplifiers, 4 single-ended programmable gain amplifiers, 4 general purpose comparators, 3 phase comparators, 10 protection comparators, and one buffer output.
Page 43: System Block Diagram
DAxN ADC MUX OFFSET AMPx BUF6 COMPARATOR TEMP MON, REF, CMPx DINx THREF AFE I/O DINx AIOx CONTROL PHASE COMPARATOR DINx PHCx PHASE IRQ2/POS PHASE PUSH PHCx BUTTON -43- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 44: Enabling The Cafe
Hibernate wake-up using Push-Button When the PAC5526 is in hibernate mode, the AIO6 push-button may be used to wake up the device. To enable the push-button wake-up using AIO6, the device must be in AIO6 special mode with the push-button enabled.
Page 45: Dac Output
SOC.MISC.VREFSET (2.5V or 3.0V) to be output on AB5. 9.10 Hard Reset A hard reset of the PAC5526 may be performed by pulling the AIO6 input low for more than 8 seconds when the AIO6 push-button mode is enabled. When this is detected, the reset signal to the MCU will be asserted and SOC.STATUS.HWRSTAT will be set to 1b to indicate this condition.
Page 46: Aio10
SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO1.HP10EN Gate CFGAIO1.HP10PREN HPROT10 Driver HP10 PROTINTM.HP10INTEN PROTSTAT.HP10INT HPDAC* IRQ1 SIGINTF.HP10STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -46- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 47: Aio1, Aio0 Digital I/O Mode
When the ADC is in automatic mode and the DTSE is active, the EMUX is used to communicate data to the CAFE to select the ADC AFE MUX channel as well as activate and deactivate the sample and hold -47- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 48: Aio1, Aio0 Protection
SOC.CFGAIO0.LP10EN may be used to enable LP10 comparator with different blanking times. Set SOC.SIGSET.LPROTHYS to 1b to enable LP10 comparator hysteresis. The output of LP10 comparator can be configured to trigger protection signal PR using SOC.CFGAIO1.LP10PREN. -48- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 49 The output of LP10 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.LP10INTEN to 1b. The real-time status can be observed using SOC.SIGINTF.LP10STAT and the latched interrupt status can be observed using SOC.PROTSTAT.LP10INT. -49- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 50: Aio32
SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO3.HP32EN Gate HPROT32 CFGAIO3.HP32PREN Driver HP10 PROTINTM.HP32INTEN PROTSTAT.HP32INT HPDAC* IRQ1 SIGINTF.HP32STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -50- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 51: Aio3, Aio2 Digital I/O Mode
When the ADC is in automatic mode and the DTSE is active, the EMUX is used to communicate data to the CAFE to select the ADC AFE MUX channel as well as activate and deactivate the sample and hold -51- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 52: Aio3, Aio2 Protection
SOC.CFGAIO2.LP32EN may be used to enable LP32 comparator with different blanking times. Set SOC.SIGSET.LPROTHYS to 1b to enable LP32 comparator hysteresis. The output of LP32 comparator can be configured to trigger protection signal PR using SOC.CFGAIO3.LP32PREN. -52- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 53: Aio2/Aio7 Buffer
SOC.PROTSTAT.LP32INT. 9.13.6 AIO2/AIO7 Buffer There is an output buffer that may be used for either AIO2 or AIO7 in the PAC5526 CAFE. To enable this buffer, set SOC.DOUTSIG1.AIOBUFEN = 1b. The input signal for this buffer may be selected by using SOC.DOUTSIG1.AIOBUFSELIN with the values below.
Page 54: Aio54
SIGSET.LPDACAB3 SIGSET.LPROTHYS Protection Mask CFGAIO5.HP54EN Gate CFGAIO5.HP54PREN HPROT54 Driver HP10 PROTINTM.HP54INTEN PROTSTAT.HP54INT HPDAC* IRQ1 SIGINTF.HP54STAT SIGSET.HPDACAB2 SIGSET.HPROTHYS HPDACH ABUS HPDACL * Common DAC for AIO10, AIO32 and AIO54 -54- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 55: Aio5, Aio4 Digital I/O Mode
When the ADC is in automatic mode and the DTSE is active, the EMUX is used to communicate data to the CAFE to select the ADC AFE MUX channel as well as activate and deactivate the sample and hold -55- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 56: Aio5, Aio4 Protection
SOC.CFGAIO5.LP54EN may be used to enable LP54 comparator with different blanking times. Set SOC.SIGSET.LPROTHYS to 1b to enable LP54 comparator hysteresis. The output of LP54 comparator can be configured to trigger protection signal PR using SOC.CFGAIO5.LP54PREN. -56- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 57 The output of LP54 can also trigger the IRQ1 interrupt by setting SOC.PROTINTEN.LP54INTEN to 1b. The real-time status can be observed using SOC.PROTSTAT.LP54STAT and the latched interrupt status can be observed using SOC.PROTSTAT.LP54INT. -57- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 58: Aio6
AIO6 may be configured as a digital input, single-ended programmable gain amplifier, comparator, output from analog ABUS or as a push-button input to wake up the device from total hibernate mode. -58- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 59: System Block Diagram
CFGAIO6.MODE6 CFGAIO6.SWAP AMUX AIO6 Push Button Mode PB Wake Up IRQ1 5.5V STATUS.PBSTAT 0.5mA STATUS.PBSTAT_LATCH MISC.PBEN Power Wake-up MISC.PB_POL Manager MISC.TPBD 300k VREF Output CFGIO1.VREFBP VREF ABUS MISC.VREFSET -59- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 60: Aio6 Digital I/O Mode
The output polarity of the comparator may be selected by using SOC.CFGAIO6.POL6 (0b: active-high; 1b: active-low). The output of the comparator may be sent to the digital bus DB1 to DB7 or to SOC.DINSIG1.DIN6 by using SOC.CFGAIO6.MUX6. -60- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 61: Aio6 Special Mode
To configure the ABUS input to the AIO6 special mode buffer (AB1 – AB7), use SOC.CFGAIO6.MUX6. The SOC.CFGAIO6.SWAP to 1b to swap the random offset of the buffer for calibration. -61- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 62: Aio7
® Power Application Controller 9.16 AIO7 AIO7 may be configured as a digital input/output, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -62- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 63: System Block Diagram
ABUS CFGAIO7.POL7 AIO8 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN7 SPECCFG2.SMUXAIO7 SIGINTF.AIO7INT BLANKING.BLANKTIME SIGINTM.AIO7REINTEN SIGINTM.AIO7FEINTEN BLANKING.BLANKMODE SPECCFG0.HYSMODE SPECCFG0.AIO7HYS CFGAIO7.MODE7 EMUX IRQ2 DOUTSIG1.AIOBUFSELOUT AIO2/7 Buffer AB[6:4] ABUS DOUTSIG1.AIOBUFSELIN DOUTSIG1.AIOBUFEN AIO2 -63- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 64: Aio7 Digital I/O Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.16.4.2 Comparator Configuration The AIO7 comparator has programmable blanking time and hysteresis modes. -64- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 65: Aio7 Special Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.16.5.2 Comparator Configuration The AIO7 comparator has programmable blanking time and hysteresis modes. -65- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 66 To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -66- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 67: Aio2/Aio7 Buffer
Power Application Controller 9.16.6 AIO2/AIO7 Buffer There is an output buffer that may be used for either AIO2 or AIO7 in the PAC5526 CAFE. To enable this buffer, set SOC.DOUTSIG1.AIOBUFEN = 1b. The input signal for this buffer may be selected by using SOC.DOUTSIG1.AIOBUFSELIN with the values below.
Page 68: Aio8
® Power Application Controller 9.17 AIO8 AIO8 may be configured as a digital input, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -68- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 69: System Block Diagram
CFGAIO9.MODE9[1] CFGAIO9.MUX9[0] CFGAIO8.OPT8[0] CFGAIO8.OPT8[1] CMP Polarity AB<3:1> IRQ2/POS ABUS CFGAIO8.POL8 AIO7 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN8 SIGINTF.AIO8INT SPECCFG2.SMUXAIO8 SIGINTEN.AIO8REINTEN BLANKING.BLANKTIME SIGINTEN.AIO8FEINTEN BLANKING.BLANKMODE SPECCFG0.HYSMODE SPECCFG1.AIO8HYS CFGAIO8.MODE8 EMUX IRQ2 -69- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 70: Aio8 Digital I/O Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.17.4.2 Comparator Configuration The AIO8 comparator has programmable blanking time and hysteresis modes. -70- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 71: Aio8 Special Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.17.5.2 Comparator Configuration The AIO8 comparator has programmable blanking time and hysteresis modes. -71- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 72 To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -72- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 73: Aio9
® Power Application Controller 9.18 AIO9 AIO9 may be configured as a digital input, single-ended programmable gain amplifier, comparator or a BEMF zero-cross comparator. -73- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 74: System Block Diagram
CFGAIO9.MODE9[1] CFGAIO9.MUX9[0] CFGAIO8.OPT8[0] CFGAIO8.OPT8[1] CMP Polarity AB<3:1> IRQ2/POS ABUS CFGAIO9.POL9 AIO8 AIO9 CFGAIO9.OPT9 VTHREF DOUTSIG0.VTHREF Input DINSIG1.DIN9 SIGINTF.AIO9INT SPECCFG2.SMUXAIO9 BLANKING.BLANKTIME SIGINTEN.AIO9REINTEN SIGINTEN.AIO9FEINTEN BLANKING.BLANKMODE SPECCFG0.HYSMODE SPECCFG1.AIO9HYS EMUX IRQ2 IRQ2 -74- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 75: Aio9 Digital I/O Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.18.4.2 Comparator Configuration The AIO9 comparator has programmable blanking time and hysteresis modes. -75- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 76: Aio9 Special Mode
SOC.DOUTSIG0.VTHREF to select a value from the following: • 00b: 0.1V • 01b: 0.2V • 10b: 0.5V • 11b: 1.25V 9.18.5.2 Comparator Configuration The AIO9 comparator has programmable blanking time and hysteresis modes. -76- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 77 To configure IRQ2/POS to be the POS position as described above, set SOC.CFGAIO8.OPT8[0] to 0b. To configure IRQ/POS to be the IRQ2 signal, set SOC.CFGAIO8.OPT8[0] to be 1b. -77- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 78: Register Summary
AIO Data Output 1 0x00 0x1B SOC.DINSIG0 AIO Data Input 0 0x00 0x1C SOC.DINSIG1 AIO Data Input 1 0x00 0x1D SOC.CFGIO1 AIO10-AIO13 Configuration 0 0x00 0x1F SOC.SIGINTEN AIO Interrupt Enable 0x00 -78- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 79 0x23 SOC.SPECCFG1 AIO8/AIO9 Hysteresis Configuration 0x00 0x24 SOC.SPECCFG2 AIO7/AIO8 Comparator Input MUX Configuration 0x00 0x25 SOC.SPECCFG3 AIO9 Comparator Input MUX Configuration 0x00 0x26 SOC.GP0 General-purpose register space 0x00 -79- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 80: Register Detail
100b: DB4 00b: Disabled 101b: DB5 01b: Enabled with 1µs blanking time 110b: DB6 10b: Enabled with 2µs blanking time 111b: DB7 11b: Enabled with 4µs blanking time -80- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 81: Soc.cfgaio1
00b: Disabled 100b: DB4 01b: Enabled with 1µs blanking time 101b: DB5 10b: Enabled with 2µs blanking time 110b: DB6 11b: Enabled with 4µs blanking time 111b: DB7 -81- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 82: Soc.cfgaio2
00b: Disabled 100b: DB4 01b: Enabled with 1µs blanking time 101b: DB5 10b: Enabled with 2µs blanking time 110b: DB6 11b: Enabled with 4µs blanking time 111b: DB7 -82- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 83: Soc.cfgaio3
00b: Disabled 100b: DB4 01b: Enabled with 1µs blanking time 101b: DB5 10b: Enabled with 2µs blanking time 110b: DB6 11b: Enabled with 4µs blanking time 111b: DB7 -83- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 84: Soc.cfgaio4
00b: Disabled 100b: DB4 01b: Enabled with 1µs blanking time 101b: DB5 10b: Enabled with 2µs blanking time 110b: DB6 11b: Enabled with 4µs blanking time 111b: DB7 -84- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 85: Soc.cfgaio5
00b: Disabled 100b: DB4 01b: Enabled with 1µs blanking time 101b: DB5 10b: Enabled with 2µs blanking time 110b: DB6 11b: Enabled with 4µs blanking time 111b: DB7 -85- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 86: Soc.cfgaio6
100b: DB4 100b: DB4 101b: AB5 101b: AB5 101b: DB5 101b: DB5 110b: AB6 110b: AB6 110b: DB6 110b: DB6 111b: AB7 111b: AB7 111b: DB7 111b: DB7 -86- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 87: Soc.cfgaio7
011b: DB3 011b: AB3 100b: DB4 100b: DB4 100b: AB4 101b: DB5 101b: DB5 101b: AB5 110b: DB6 110b: DB6 110b: AB6 111b: DB7 111b: DB7 111b: AB7 -87- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 88: Soc.cfgaio8
011b: AB3 011b: DB3 100b: DB4 100b: AB4 100b: DB4 101b: DB5 101b: AB5 101b: DB5 110b: DB6 110b: AB6 110b: DB6 111b: DB7 111b: AB7 111b: DB7 -88- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 89: Soc.cfgaio9
100b: AB4 100b: DB4 101b: DB5 MUX9[0]: Switch POS after MUX 101b: AB5 101b: DB5 110b: DB6 to DB6. 110b: AB6 110b: DB6 111b: DB7 111b: AB7 111b: DB7 -89- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 90: Soc.sigset
0b: LPDAC output not connected to AB3 1b: LPDAC output connected to AB3 Connect HPDAC output to AB2: HPDACAB2 0b: HPDAC output not connected to AB2 1b: HPDAC output connected to AB2 -90- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 91: Soc.hpdach
LPDAC MSB setting bits 9:2 9.20.15 SOC.LPDACL Register 9-15 SOC.LPDAC1 (LPDAC Low Setting, 14h) NAME ACCESS RESET DESCRIPTION Reserved Reserved, write to 0. LPDAC[1:0] LPDAC Setting bits 1:0 -91- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 92: Soc.shcfg1
DAO32 Sample and Hold output sync to AFE ADC MUX: DAO32SH 0b: Bypass S/H 1b: enable S/H DAO10 Sample and Hold output sync to AFE ADC MUX: DAO10SH 0b: Bypass S/H 1b: enable S/H -92- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 93: Soc.shcfg2
0110b: AB4 0111b: AB5 1000b: AB6 1001b: AB7 1010b: AB8 1011b: AB9 1100b: AB10 (VPTAT) 1101b: AB11 (PWRMON) 1110b: AB12 (VP / 10) 1111b: AB13 (VM / 20) -93- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 94: Soc.protinten
Reserved, write to 0. LPROT54 Interrupt enable: LP54INTEN 0b: disabled 1b: enabled LPROT32 Interrupt enable: LP32INTEN 0b: disabled 1b: enabled LPROT10 Interrupt enable: LP10INTEN 0b: disabled 1b: enabled -94- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 95: Soc.protstat
1b: Interrupt, write 1 to clear LPROT32 Interrupt: LP32INT 0b: No interrupt 1b: Interrupt, write 1 to clear LPROT10 Interrupt: LP10INT 0b: No interrupt 1b: Interrupt, write 1 to clear -95- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 96: Soc.doutsig0
Data output to AIO5. DOUT4 Data output to AIO4. DOUT3 Data output to AIO3. DOUT2 Data output to AIO2. DOUT1 Data output to AIO1. DOUT0 Data output to AIO0. -96- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 97: Soc.doutsig1
Enable AIO2/AIO7 buffer. AIOBUFEN 0b: Not enabled 1b: Enabled DOUT9 Data output to AIO9. DOUT8 Data output to AIO8. DOUT7 Data output to AIO7. DOUT6 Data output to AIO6. -97- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 98: Soc.dinsig0
DRV_FLT 0b: No fault detected 1b: Fault detected DIN9 Data input from AIO9. DIN8 Data input from AIO8. DIN7 Data input from AIO7. DIN6 Data input from AIO6. -98- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 99: Soc.cfgio1
Enable AIO6 comparator output to disable gate driver on EN_AIO6_OCP OC event. Switch VREF signal to AB5 so that it can be buffered out VREFBP on AIO6. 000b Reserved, write as 0. -99- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 100: Soc.siginten
0b: disabled 1b: enabled AIO7 digital input falling edge interrupt enable. AIO7FEINTEN 0b: disabled 1b: enabled AIO6 digital input falling edge interrupt enable. AIO6FEINTEN 0b: disabled 1b: enabled -100- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 101: Soc.sigintf
AIO7 Interrupt: AIO7INT 0b: No Interrupt 1b: Interrupt, IRQ2 asserted. Write 1b to clear. AIO6 Interrupt: AIO6INT 0b: No Interrupt 1b: Interrupt, IRQ2 asserted. Write 1b to clear. -101- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 102: Soc.blanking
1110b: 5500ns 1111b: 6000ns Reserved, write as 0. BEMF Comparator Blanking Mode: 00b: Disabled BLANKMODE 01b: Leading edge blanking 10b: Trailing edge blanking 11b: Leading and trailing edge blanking -102- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 103: Soc.speccfg0
1100b: Rising = 80mV, Falling = 0mV 1101b: Rising = 80mV, Falling = 20mV 1110b: Rising = 80mV, Falling = 40mV 1111b: Rising = 80mV, Falling = 80mV -103- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 104: Soc.speccfg1
1011b: Rising = 10mV, Falling = 20mV 1100b: Rising = 20mV, Falling = 0mV 1101b: Rising = 20mV, Falling = 5mV 1110b: Rising = 20mV, Falling = 10mV -104- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 105 1100b: Rising = 80mV, Falling = 0mV 1101b: Rising = 80mV, Falling = 20mV 1110b: Rising = 80mV, Falling = 40mV 1111b: Rising = 80mV, Falling = 80mV -105- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 106: Soc.speccfg2
001b: AB1 (virtual center-tap) 010b: AB2 SMUXAIO9 000b 011b: AB3 100b: AIO7 (phase to phase compare) 101b: AIO8 (phase to phase compare) 110b: RFU 111b: RFU 000b Reserved, write to 0. -106- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 107: Soc.gp0
® Power Application Controller 9.20.33 SOC.GP0 Register 9-32 SOC.GP0 (General-Purpose Register Space, 26h) NAME ACCESS RESET DESCRIPTION General-purpose, read-write register. -107- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 108: Application Specific Power Driver
3 high-side gate drivers with programmable gate driving up to 1A ▪ 3 low-side gate drivers with programmable gate driving up to 1A ▪ 100% duty cycle ▪ Cycle-by-cycle current limit ▪ Configurable fault protection ▪ Short-circuit detection -108- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 109: System Block Diagram
Figure 10-1 ASPD System Block Diagram APPLICATION SPECIFIC POWER DRIVERS HIGH-SIDE GATE DRIVERS LEVEL PRE- DRHx SHIFT DRIVER DRSx FAULT PROTECT & CURRENT LIMIT LOW-SIDE GATE DRIVERS Driver Enable PRE- DRLx DRIVER -109- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 110: Functional Description
The input to the 3 high-side gate drivers are shown below: • DRH0: PB4 (PWMA4) • DRH1: PB5 (PWMA5) • DRH2: PB6 (PWMA6) -110- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 111: Low-Side Gate Drivers
The input to the 3 high-side gate drivers are shown below: • DRL0: PB0 (PWMA4) • DRL1: PB1 (PWMA5) • DRL2: PB2 (PWMA6) -111- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 112: Enabling The Aspd
Once the gate drivers have been disabled, the MCU must reset the ASPD by setting SOC.ENDRV.ENDRV to 0b, then back to 1b in order to re-enable the ASPD. -112- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 113: Cycle By Cycle Current Limit
During operation, if the PWMCBC signal is high, then the output to the configured gate drivers is temporarily disabled, until the PWMCBC becomes available again. The following shows which drivers are disabled during this condition: -113- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 114 If CFGDRV2.LPCBCLS = 1b and CFGDRV2.nDRV41DISM = 1b, disable DRL1 PWMCBC = high: • If CFGDRV2.LPCBCHS = 1b and CFGDRV2.nDRV30DISM = 1b, disable DRH3 • If CFGDRV2.LPCBCLS = 1b and CFGDRV2.nDRV30DISM = 1b, disable DRL0 -114- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 115: Gate Driver Short Protection
UVLOF;VP POKF;VP 10.12 Break-before-make Configuration The PAC5526 contains support for “break-before-make” gate driver safety. When SOC.CFGDRV4.ENBBM is set to 1b, then the gate driver will force a 100ns dead-time in between the half-bridge complementary gate drivers (DRH0/DRL0, DRH1/DRL1, DRH2/DRL2). Note that this safety check is in addition to the programmable dead-time that the MCU inserts between the high-side and low-side gate driver inputs.
Page 116: Gate Driver Programmable Current
Power Application Controller 10.13 Gate Driver Programmable Current The PAC5526 high-side and low-side gate drivers support programmable current output. This allows the gate driver to internally control the slew rate to the MOSFET gate, which eliminates the need for external series components to control the slew rate.
Page 117: Figure 10-6 Low-Side Gate Driver Waveforms
This is the amount of time from the input PWM edge transition during which the current is controlled. The duration of the controlled current may be set according to the following table. -117- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 118: Table 10-1 Aspd Controlled-Current Time Configuration
Low-side gate driver source current: DRVILIMLS.LSSOURCE • Low-side gate driver sink current: DRVILIMLS.LSSINK The source and sink current that is applied during this time is shown in the following table. -118- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 119: Table 10-2 Aspd Controlled-Current Time Configuration
Table 10-2 ASPD Controlled-Current Time Configuration Register Value Time Duration 000b 250mA 001b 350mA 010b 450mA DRVILIMHS.HSSOURCE 011b 550mA DRVILIMHS.HSSINK DRVILIMLS.LSSOURCE 100b 650mA DRVILIMLS.LSSINK 101b 750mA 110b 850mA 111b 1000mA -119- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 120: Register Summary
Low-side Driver Current Limit Configuration SOC.DRVILIMH High-side Driver Current Limit Configuration SOC.CFGDRV4 Driver Configuration 4 0x00 SOC.DRV_FLT Driver Fault Status SOC.ENDRV Driver Manager Enable SOC.WDTPASS SOC Watchdog Timer Password -120- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 121: Register Detail
110b: 0.75µs 111b: 0.55µs High side PR protection enable: HSPREN 0b: PR disabled 1b: PR enabled Low side PR protection enable: LSPREN 0b: PR disabled 1b: PR enabled -121- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 122: Soc.cfgdrv2
0b: Do not disable 1b: Disable when commanded Control signal for high-side gate drivers disable. Used for PWM pulse cycle-by-cycle current limit: LPCBCHS 0b: Do not disable 1b: Disable when commanded -122- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 123: Soc.cfgdrv3
0b: masked 1b: not masked Mask signal for LPROT10 for PWM pulse cycle-by-cycle current limit: nLP10CBCM 0b: masked 1b: not masked Reserved, write as 0. -123- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 124: Soc.statdrv
1b: Driver disable event occurred Latched status of DRV10DIS signal. To clear, write this bit to a 1b: DRV10DIS 0b: No driver disable event 1b: Driver disable event occurred -124- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 125: Soc.drvilimls
Reserved, write as 0b. Low-side gate driver programmable source current: 000b: 250mA 001b: 350mA 010b: 450mA LSSOURCE 000b 011b: 550mA 100b: 650mA 101b: 750mA 110b: 850mA 111b: 1000mA -125- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 126: Soc.drvilimhs
Reserved, write as 0b High-side gate driver programmable source current: 000b: 250mA 001b: 350mA 010b: 450mA HSSOURCE 000b 011b: 550mA 100b: 650mA 101b: 750mA 110b: 850mA 111b: 1000mA -126- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 127: Soc.cfgdrv4
This is the real-time status of the charge pump fault. When the charge pump is disabled, this value will be 0b. Driver fault flag: DRV_FLT 0b: no flag 1b: flag -127- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 128: Soc.endrv
1b: Enable 10.15.10 SOC.WDTPASS Register 10-10 SOC.WDTPASS (WDT Password, 7Eh) NAME ACCESS RESET DESCRIPTION WDTPASS 0000 0000b To reset the SOC Watchdog Timer, write this field to ACh. -128- Copyright 2020 © Qorvo, Inc. Rev 1.0 – Jan 17, 2020...
Page 129: Legal Information
PURPOSE. Without limiting the generality of the foregoing, Qorvo products are not warranted or authorized for use as critical components in medical, life-saving, or life-sustaining applications, or other applications where a failure would reasonably be expected to cause severe personal injury or death.

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