User Manuals: Qorivva MPC5 Series Microcontrollers

Manuals and User Guides for Qorivva MPC5 Series Microcontrollers. We have 1 Qorivva MPC5 Series Microcontrollers manual available for free PDF download: Manual

Qorivva MPC5 Series Manual (166 pages)

Debugger and NEXUS Trace

Brand: Qorivva | Category: Microcontrollers | Size: 1 MB

Table of Contents
1
Qorivva Mpc5Xxx/Spc5Xx Debugger and NEXUS Trace
1
Introduction
8
Available Tools
8
Jtag/Once Debugger
8
On-Chip Trace
9
High-Speed Serial Off-Chip Trace (Aurora NEXUS)
9
Parallel Off-Chip Trace (Parallel NEXUS)
10
Co-Processor Debugging (Etpu/Gtm/Spt)
10
Multicore Debugging
10
Software-Only Debugging (Hostmci) Via XCP
10
Software Installation
11
Hardware Installation
12
JTAG Debugger
12
Parallel Nexus Debugger and Trace
13
Aurora Nexus Debugger and Trace
14
ESD Protection Considerations
15
Demo and Start-Up Scripts
15
Debug Cable / Nexus Adapter Versions and Detection
16
Brief Overview of Documents for New Users
17
Target Design Requirement/Recommendations
18
General (ICD Debugger)
18
Quick Start
19
Run Program from On-Chip SRAM
19
Run Program from FLASH
21
Connect to Running Program (Hot Plug-In)
22
Faq
23
Debugging
24
Breakpoints
24
Software Breakpoints
24
On-Chip Breakpoints
24
Breakpoints on Program Addresses
25
Breakpoints on Data Addresses
26
Breakpoints on Data Access at Program Address
27
Breakpoints on Data Value
27
Counting Debug Events with Core Performance Monitor
28
Memory Access
29
Access Classes
29
Access Classes to Memory and Memory Mapped Resources
29
Access Classes to Other Addressable Core and Peripheral Resources
30
Cache Debugging Support
32
Memory Coherency
32
Memory Coherency During Run-Time Memory Access
32
Viewing Cache Contents
33
MESI States and Cache Status Flags
34
Using Cache Lines as SRAM Extension
34
Support for Peripheral Modules
35
Displaying Peripheral Module Registers
35
Peripheral Registers Modified by TRACE32
36
Debugging and Tracing through Reset
37
Multicore Debugging
39
SMP Debugging
40
AMP Debugging
41
Watchdog Timer Support
42
E200 Core Watchdog (TCR/TSR)
42
On-Chip Watchdog (SWT)
42
Chip External Watchdog
43
Censorship Unlock
44
Censorship Unlock on MPC56XX and SPC56X Processors
44
Censorship Unlock on MPC57XX, SPC57X/SPC58X and S32R Processors
44
Recovering a Censored Processor (MPC57XX, SPC57X/SPC58X and S32R)
46
Non-Secure Boot (S32R294)
48
Non-Secure Boot by Script
48
Non-Secure Boot if Fuses Blown
48
Troubleshooting Debug
49
Tracing
51
E200 PCFIFO On-Chip Trace
51
MPC57XX/SPC57X/SPC58X NEXUS On-Chip Trace (Trace-To-Memory)
51
External Trace Ports (Parallel Nexus/Aurora NEXUS)
53
Basic Setup for Parallel Nexus
53
Basic Setup for Aurora Nexus
53
Tracing the Program Flow
54
Tracing of Data (Read/Write) Transactions
55
Example: Data Trace with Address Range
55
Tracing of Context Switches
55
Trace Context Switches Using Data Trace Messaging (DTM)
55
Trace Context Switch Using Ownership Trace Messaging (OTM)
56
Trace Based Run-Time Measurement / Timestamping
56
Trace Based Run-Time Measurement for Off-Chip Parallel NEXUS
57
Trace Based Run-Time Measurement for Off-Chip Aurora NEXUS
57
Trace Based Run-Time Measurement for On-Chip Trace / Trace-To-Memory
57
Correlation of the Trace Timestamp with Other Tool Timestamps
58
Implications of Using the Processor Generated Timestamps
58
Processors with On-Chip Timestamp Support
59
Trace Filtering and Triggering with Debug Events
59
Overview
59
Example: Selective Program Tracing
61
Example: Event Controlled Program/Data Trace Start and End
62
Example: Event Controlled Trace Recording
63
Example: Event Controlled Trigger Signals
63
Example: Event Counter
64
Tracing Peripheral Modules / Bus Masters
64
Example: Filter by Address Range
64
Example: Event Controlled Trace Start and End
64
Trace Filtering and Triggering Features Provided by TRACE32
65
Troubleshooting Trace
65
Tracing VLE or Mixed FLE/VLE Applications
65
FLASH Programming Support
67
FLASH Programming Scripts
67
Requirements Due to FLASH ECC Protection
69
Programming the RCHW or Boot Header
70
Programming the Shadow Row
70
Programming Serial Boot Password and Censorship Word
72
TEST / UTEST / OTP FLASH Programming
73
Programming an OTP Sector
73
Programming an UTEST Sector Which Is Not Set to OTP
74
Brownout Depletion Recovery
75
Troubleshooting FLASH
75
Command Reference: System Commands
77
System.bdmclock
77
Set BDM Clock Frequency
77
System.config.state
78
Display Target Configuration
78
System.config
79
Configure Debugger According to Target Topology
79
System.config.debugporttype Set Debug Cable Interface Mode
84
Hardware Requirements for Cjtag Operation
84
System.config.extwdtdis
85
Disable External Watchdog
85
System.config Portsharing
86
Control Sharing of Debug Port with Other Tool
86
System.cpu
86
Select the Target Processor
86
System.lock
87
Lock and Tristate the Debug Port
87
System.memaccess
87
Run-Time Memory Access (Non-Intrusive)
87
System.mode
89
Select Operation Mode
89
Command Reference: System.option Commands
90
System.option BISTRUN
90
Debug with bist Enabled
90
System.option Corestandby
90
On-The-Fly Breakpoint and Trace Setup
90
System.option DCFREEZE
90
Data Cache State Frozen While Core Halted
90
System.option DCREAD
91
Read from Data Cache
91
System.option Disableresetescalation
91
Control Reset Escalation Disabling
91
System.option Disableshortsequence
92
Short Reset Sequence Handling
92
System.option Dismode
92
Disassembler Operation Mode
92
System.option DUALPORT
93
Implicitly Use Run-Time Memory Access
93
System.option FASTACCESS Special Operation Mode for Fast Run Control
94
System.option FREEZE Freeze System Timers on Debug Events
94
System.option Holdreset
95
Set Reset Hold Time
95
System.option ICFLUSH
95
Invalidate Instruction Cache before Go and Step
95
System.option ICREAD
95
Read from Instruction Cache
95
System.option IMASKASM
96
Disable Interrupts While Single Stepping
96
System.option IMASKHLL
96
Disable Interrupts While HLL Single Stepping
96
System.option KEYCODE
96
Inhibit Censorship Protection
96
System.option Lpmdebug
98
Enable Low Power Mode Debug Handshake
98
System.option Lockstepdebug
99
Enable Lock-Step Core Register Access
99
System.option MMUSPACES
99
Separate Address Spaces by Space Ids
99
System.option Nexusmemorycoherency
100
Coherent NEXUS Mem-Access
100
System.option Nodebugstop
101
Disable JTAG Stop on Debug Events
101
System.option Nojtagrdy
101
Do Not Evaluate JTAG_RDY Signal
101
System.option NOTRAP
102
Use Brkpt Instruction for Software Breakpoints
102
System.option OVERLAY
103
Enable Overlay Support
103
System.option PC
103
Set Fetch Address Debug Actions
103
System.option Resetbehavior
104
Set Behavior When Target Reset Detected
104
System.option Resbreak
104
Halt the Core While Reset Asserted
104
System.option Resetdetection
105
Configure Reset Detection Method
105
System.option Resetmode
106
Select Reset Mode for System.up
106
System.option SLOWRESET
107
Relaxed Reset Timing
107
System.option STEPSOFT
107
Use Alternative Method for ASM Single Step
107
System.option Tdoselect
107
Select TDO Source of Lock Step Core Pair
107
System.option VECTORS
107
Specify Interrupt Vector Table Address
107
System.option Waitreset
109
Set Reset Wait Time
109
System.option WATCHDOG
110
Debug with Software Watchdog Timer
110
Command Reference: MMU Commands
112
Mmu.dump
112
Page Wise Display of MMU Translation Table
112
Mmu.list
114
Compact Display of MMU Translation Table
114
Mmu.scan
116
Load MMU Table from CPU
116
Mmu.set
117
Set an MMU TLB Entry
117
Command Reference: Benchmarkcounter
118
Bmc.<Counter>.Atob
118
Enable Event Triggered Counter Start and Stop
118
Bmc.<Counter>.Freeze Freeze Counter in Certain Core States
121
Bmc.freeze
122
Freeze Counters While Core Halted
122
Command Reference: Tronchip
123
Tronchip.convert
123
Adjust Range Breakpoint in On-Chip Resource
123
Tronchip.edbrac0
124
Assign Debug Events to Target Software
124
Tronchip.evten
125
Enable EVTI and EVTO Pins
125
Tronchip.reset
126
Reset On-Chip Trigger Settings
126
Tronchip.set
126
Enable Special On-Chip Breakpoints
126
Tronchip.varconvert
127
Set Single Address Breakpoint for Scalar
127
Tronchip.state
128
View On-Chip Trigger Setup Window
128
Command Reference: Onchip
129
Onchip.tbarange
129
Set On-Chip Trace Buffer Address Range
129
Command Reference: NEXUS
130
Nexus.btm
130
Enable Program Trace Messaging
130
Nexus.client<X>.Bussel
130
Set NXMC Target RAM
130
Nexus.client<X>.Mode
130
Set Data Trace Mode of Nexus Client
130
Nexus.client<X>.Select
131
Select a Nexus Client for Data Tracing
131
Nexus.client3.Sptacqmaster
131
Trace Individual SPT Masters
131
Nexus.coreenable
131
Enable Core Tracing for Dedicated Cores in SMP
131
Nexus.ddr
132
Enable NEXUS Double Data Rate Mode
132
Nexus.dmadtm
132
Enable DMA Data Trace Messaging
132
Nexus.dtm
133
Enable Data Trace Messaging
133
Nexus.dtmark
133
Data Trace Mark
133
Nexus.dtmwhilehalted
134
Data Trace Messaging While Core Halted
134
Nexus.dqm
134
Enable Data Acquisition Messaging
134
Nexus.fraydtm
134
Enable Flexray Data Trace Messaging
134
Nexus.htm
135
Enable Branch History Messaging
135
Nexus.off
135
Switch the NEXUS Trace Port off
135
NEXUS.ON Switch the NEXUS Trace Port on
136
Nexus.otm
137
Enable Ownership Trace Messaging
137
Nexus.pcrconfig
137
Configure NEXUS PCR for Tracing
137
Nexus.pincr
138
Define DCI PINCR Register Value
138
Nexus.portmode
138
Set NEXUS Trace Port Frequency
138
Nexus.portsize
139
Set Trace Port Width
139
Nexus.potd
139
Periodic Ownership Trace Disable
139
Nexus.ptcm
140
Enable Program Trace Correlation Messages
140
Nexus.ptmark
140
Program Trace Mark
140
Nexus.refclock
141
Enable Aurora Reference Clock
141
Nexus.register
141
Display NEXUS Trace Control Registers
141
Nexus.reset
141
Reset NEXUS Trace Port Settings
141
Nexus.rfmhistbugfix
141
Double RFM Workaround
141
Nexus.smarttrace
142
Enable Smart Trace Analysis
142
Nexus.spen<Messagetype
142
Enable Message Suppression
142
Nexus.stall
142
Stall the Program Execution When FIFO Full
142
Nexus.state
143
Display NEXUS Port Configuration Window
143
Nexus.supprthreshold
143
Set Fill Level for Message Suppression
143
Nexus.timestamps
143
Enable On-Chip Timestamp Generation
143
Nexus.wtm
144
Enable Watchpoint Messaging
144
Nexus Specific Tronchip Commands
145
Tronchip.alpha
145
Set Special Breakpoint Function
145
Tronchip.beta
145
Tronchip.charly
146
Set Special Breakpoint Function
146
Tronchip.delta
146
Tronchip.disable
146
Disable NEXUS Trace Register Control
146
Tronchip.echo
146
Tronchip.enable
147
Enable NEXUS Trace Register Control
147
Tronchip.evti
147
Allow the EVTI Signal to Stop the Program Execution
147
Tronchip.evto
147
Use EVTO Signal for Runtime Measurement
147
Tronchip.external
148
Enable Trace Trigger Input of NEXUS Adapter
148
Tronchip.out0
148
Select OUT0 Pin Signal Source
148
Tronchip.out1
149
Select OUT1 Pin Signal Source
149
Tronchip.toolio2
150
Select TOOLIO2 Pin Signal Source
150
Tronchip.tracecontrol
151
Trace Control with Special Debug Events
151
Debug and Trace Connectors
152
14-Pin Jtag/Once Connector (JTAG)
152
AUTO26 Connector (JTAG)
152
10-Pin ECU14 Connector (with Converter LA-3843)
153
38-Pin Mictor Connector (NEXUS Parallel)
153
50-Pin SAMTEC ERF8 Connector (NEXUS Parallel)
154
51-Pin Glenair / ROBUST Connector (NEXUS Parallel)
155
34-Pin SAMTEC ERF8 Connector (Aurora NEXUS)
156
Mechanical Dimensions
157
Technical Data
166
Operation Voltage
166
Operation Frequency
166

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