System.option Slowreset; Relaxed Reset Timing; System.option Stepsoft; Use Alternative Method For Asm Single Step - Qorivva MPC5 Series Manual

Debugger and nexus trace
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SYStem.Option SLOWRESET

Format:
Default: OFF. Set to ON to use a relaxed reset timing for processors with BIST enabled, or when debugger is
used with processor emulation systems. Deprecated, use
SYStem.Option WaitReset

SYStem.Option STEPSOFT

Format:
This method uses software breakpoints to perform an assembler single step instead of the processor's built-
in single step feature. Works only for software in RAM. Do not turn ON unless advised by Lauterbach.

SYStem.Option TDOSELect

Format:
If the processor consists of a lock-step core pair, this option defines, which core's TDO signal is routed to the
TDO pin of the processor. Can be useful for debugging lock-step related application issues. Not available for
cores in delayed lock-step. This setting should only be changed before starting the debug session, or at least
while the core is running.

SYStem.Option VECTORS

Format:
Only required for MPC5553 and MPC5554. Not required for other processors.
On MPC5553/4, indirect branch messages do not indicate if the reason was an indirect branch or an
interrupt. If the address range of the interrupt vectors are specified by this command, the TRACE32 NEXUS
debugger marks all indirect branches to these addresses / the address range as interrupt. This information is
needed for correct trace display and run-time statistic analysis.
Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 107
SYStem.Option SLOWRESET [ON | OFF] (deprecated)
instead.
SYStem.Option STEPSOFT [ON | OFF]
SYStem.Option TDOSELect [A | B]
SYStem.Option VECTORS <range> [ | <range> ...]
©1989-2021 Lauterbach GmbH
SYStem.Option HoldReset

Use alternative method for ASM single step

Select TDO source of lock step core pair

Specify interrupt vector table address

Relaxed reset timing

and

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