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Qorivva MPC5 Series Manual

Debugger and nexus trace
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Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace

TRACE32 Online Help
TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
Qorivva MPC5xxx/SPC5xx ......................................................................................................
Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace .................................................
Introduction .......................................................................................................................
Target Design Requirement/Recommendations ............................................................
Quick Start .........................................................................................................................
FAQ .....................................................................................................................................
Debugging ..........................................................................................................................
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Summary of Contents for Qorivva MPC5 Series

  • Page 1: Table Of Contents

     ICD In-Circuit Debugger ........................  Processor Architecture Manuals .................... Qorivva MPC5xxx/SPC5xx ...................... Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace ..........Introduction ........................Available Tools JTAG/OnCE Debugger On-chip Trace High-Speed Serial Off-chip Trace (Aurora NEXUS) Parallel Off-chip Trace (parallel NEXUS)
  • Page 2 MPC57XX/SPC57X/SPC58X NEXUS On-chip Trace (trace-to-memory) External Trace Ports (Parallel NEXUS/Aurora NEXUS) Basic Setup for Parallel Nexus Basic Setup for Aurora Nexus Tracing the Program Flow Tracing of Data (read/write) Transactions ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 2...
  • Page 3 Configure debugger according to target topology SYStem.CONFIG.DEBUGPORTTYPE Set debug cable interface mode Hardware Requirements for cJTAG Operation SYStem.CONFIG.EXTWDTDIS Disable external watchdog SYStem.CONFIG PortSHaRing Control sharing of debug port with other tool ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 3...
  • Page 4 Set reset wait time SYStem.Option WATCHDOG Debug with software watchdog timer Command Reference: MMU Commands ................. MMU.DUMP Page wise display of MMU translation table MMU.List Compact display of MMU translation table ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 4...
  • Page 5 Set NEXUS trace port frequency NEXUS.PortSize Set trace port width NEXUS.POTD Periodic ownership trace disable NEXUS.PTCM Enable program trace correlation messages NEXUS.PTMARK Program trace mark NEXUS.RefClock Enable Aurora reference clock ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 5...
  • Page 6 38-pin Mictor Connector (NEXUS parallel) 50-pin SAMTEC ERF8 Connector (NEXUS parallel) 51-pin GlenAir / ROBUST Connector (NEXUS parallel) 34-pin SAMTEC ERF8 Connector (Aurora NEXUS) Mechanical Dimensions ....................Technical Data ........................Operation Voltage Operation Frequency ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 6...
  • Page 7 Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace Version 30-Apr-2021 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 7...

  • Page 8: Introduction

    This document describes the processor specific settings and features for TRACE32-ICD for the following CPU families: • NXP/Freescale Qorivva MPC55XX, MPC56XX, MPC57XX and S32R (PowerPC series) • STMicroelectronics SPC56X, SPC57X and SPC58X series Please keep in mind that only the...

  • Page 9: On-Chip Trace

    Qorivva MPC57xx/SPC5XX (LA-3911) and a POWER TRACE II module. A POWERTRACE / ETHERNET module can be used with reduced speed and limited functionality. Basic Setup for Aurora Nexus for more information. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 9...

  • Page 10: Parallel Off-Chip Trace (Parallel Nexus)

    • LA-9012L: 1 User Floating License XCP MPC5xxx Debug Back-End • LA-8902L: 1 User Floating License Multicore Debugging (optional) • LA-9013L: 1 User Floating License XCP MPC5xxx Trace License (optional) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 10...

  • Page 11: Software Installation

    An installer is available for a complete TRACE32 installation under Windows. “MS Windows” in ICD Quick Installation, page 24 (icd_quick_installation.pdf). • For a complete installation of TRACE32 under Linux, see “PC_LINUX” in ICD Quick Installation, page 26 (icd_quick_installation.pdf). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 11...

  • Page 12: Hardware Installation

    Hardware Installation JTAG Debugger PC or Workstation Target Debug Cable POWER DEBUG USB INTERFACE / USB 3 Cable POWER DEBUG INTERFACE / USB 3 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 12...

  • Page 13: Parallel Nexus Debugger And Trace

    Parallel Nexus Debugger and Trace SWITCH PC or Workstation 1 GBit Ethernet Target POWER DEBUG PRO Ethernet Cable POWER TRACE II CABLE C B A NEXUS Adapter POWER DEBUG PRO POWER TRACE II ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 13...

  • Page 14: Aurora Nexus Debugger And Trace

    1 GBit Ethernet Target Debug Cable POWER DEBUG PRO Ethernet Cable POWER TRACE II Adapter CABLE C B A Extension Cable Samtec 34 Preprocessor POWER DEBUG PRO POWER TRACE II ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 14...

  • Page 15: Esd Protection Considerations

    In TRACE32, choose File menu > Run Script. Navigate to ~~/demo/powerpc/hardware/ and select your board and CPU. The demo scripts can be started through the menu MPC5XXX > Tools > Start Demo: ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 15...

  • Page 16: Debug Cable / Nexus Adapter Versions And Detection

    LA-7753 rev. 2 PRINT ID.CABLE()==0x3535 (OnCE debug cable, JTAG and cJTAG, supports reset detection) LA-7630 PRINT POWERNEXUS()&&(ID.CABLE()==0x0002) (Nexus Adapter, max 16 MDO / 2 MSEO, 1-5V, SDR and DDR) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 16...

  • Page 17: Brief Overview Of Documents For New Users

    “Debugger Basics - SMP Training” (training_debugger_smp.pdf): SMP debugging. • “eTPU Debugger and Trace” (debugger_etpu.pdf): Debugging and tracing the eTPU/eTPU2. • “GTM Debugger and Trace” (debugger_gtm.pdf): Debugging and tracing the Generic Timer Module (GTM). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 17...

  • Page 18: Target Design Requirement/Recommendations

    The T32 internal buffer/level shifter will be supplied via the VCCS pin. with blue Therefore it is necessary to reduce the VCCS pull-up on the target board to a value smaller 10 . ribbon cable ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 18...

  • Page 19: Quick Start

    For run-time memory access, the debugger requires a static translation table. As the core is halted and MMU set up, we can take the translation form the TLBs: ;copy core TLBs to debugger translation table MMU.SCAN TLB1 ;enable debugger based address translation TRANSlation.ON ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 19...
  • Page 20 Load the program. Data.LOAD.Elf demo.elf ; ELF specifies the format, ; demo.elf is the file name Run program, e.g. until function main. Go main Display ASM/HLL core at current instruction pointer List ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 20...

  • Page 21: Run Program From Flash

    As projects usually use 1:1 translation, a manual declaration can be performed. ;set up 1:1 address translation and enable TRANSlation.Create 0x00000000--0xFFFFFFFF 0x00000000 TRANSlation.ON Run program, e.g. until function main. Go main Display ASM/HLL core at current instruction pointer List ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 21...

  • Page 22: Connect To Running Program (Hot Plug-In)

    TRANSlation.Create 0x00000000--0xFFFFFFFF 0x00000000 TRANSlation.ON Observe variables or memory. Var.View %E my_var your_var Data.Dump E:0x40000100 Set breakpoints or halt core. Break.Set my_func /Onchip Break Display ASM/HLL core at current instruction pointer List ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 22...

  • Page 23: Faq

    Please refer to our Frequently Asked Questions page on the Lauterbach website. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 23...

  • Page 24: Debugging

    2 single 2 single 2 read/write breakpoints breakpoints breakpoints 2 data value -- or -- -- or -- (associated no counters 2 breakpoint 1 breakpoint with data ranges range address BPs) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 24...

  • Page 25: Breakpoints On Program Addresses

    If writing the software breakpoint fails (translation error or bus error), then an on-chip breakpoint will be set instead. If a memory range must ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 25...

  • Page 26: Breakpoints On Data Addresses

    Equal to program address breakpoints, data address breakpoints can be configured to stop if the break event occurred a given number of times: ;stop on the 8th write to arrayindex Break.Set arrayindex /Write /COUNT 20. Data address breakpoint limitations: ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 26...

  • Page 27: Breakpoints On Data Access At Program Address

    In case of the NEXUS debugger and trace, breakpoints on data value can be realized using the complex trigger unit. See “Complex Trigger Unit for Nexus MPC5xxx” (app_ctu_mpc5xxx.pdf). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 27...

  • Page 28: Counting Debug Events With Core Performance Monitor

    Var.Break.Set xval /Write /Onchip /Alpha Var.Break.Set xval /Write /Onchip /Data 0x98 /Beta ;Configure BMC (only CNT2 and CNT3 can count debug events) BMC.state BMC.CNT2.EVENT ALPHA BMC.CNT3.EVENT BETA ;Show ratio BMC.CNT3.RATIO X/CNT2 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 28...

  • Page 29: Memory Access

    L1 Instruction Cache (or L1 Unified cache) L1 Data Cache L2 Cache No Cache (access with caching inhibited) Emulation memory in MPC57XX/SPC57X emulation devices In addition to the access classes, there are access class attributes. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 29...

  • Page 30: Access Classes To Other Addressable Core And Peripheral Resources

    Device Control Register (DCR) access Access to the core’s TLB entries NEXUS register and special debug register access SPR, PMR and DCR registers are addressed by specifying the register number after the access class. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 30...
  • Page 31 Manual changes are likely to disturb debugger/trace functionality and in most cases will be overwritten by the debugger. Use the NEXUS commands to configure tracing instead of directly writing to the NEXUS registers. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 31...

  • Page 32: Cache Debugging Support

    (e200z6, e200z650, e200z750, e200z760). For cores without data cache and cores that only support write-through (like most MPC57XX/SPC57X/SPC58X), there are no restrictions to run-time memory access. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 32...

  • Page 33: Viewing Cache Contents

    Physical address of the cache line. The address is composed of cache tag and set index. set, way Set and way index of the cache v, d Status bits of the cache line v(alid), d(irty) MESI state ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 33...

  • Page 34: Mesi States And Cache Status Flags

    (bus error) if the debugger is not configured / used as described below. If the cache lines are used as data memory, ensure that SYStem.Option DCREAD is set to ON (default). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 34...

  • Page 35: Support For Peripheral Modules

    Open the peripheral registers view either using the command PER.view, or open the window by menu: CPU -> Peripherals. In order to show a certain module directly, open it by menu using MPC5XXX -> On-chip peripherals. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 35...

  • Page 36: Peripheral Registers Modified By Trace32

    Some memory mapped registers of the on-chip peripherals have to be modified to allow proper debug control of the processor: Register Feature / Action Dependencies SWT[CR] Watchdog. Must be disabled e.g. SYStem.Option WATCHDOG for FLASH programming. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 36...

  • Page 37: Debugging And Tracing Through Reset

    Most processors of the MPC56XX/SPC56XX and MPC57XX/SPC57XX series natively support debugging through reset, because the debug and trace registers are not cleared upon reset. Breakpoints and trace settings are not affected and are still in effect after a reset. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 37...
  • Page 38 ESR0 (or similar pin that only causes a functional reset), the bit for external reset is set in addition to original reset flags. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 38...

  • Page 39: Multicore Debugging

    (e.g. e200 core_0 and e200 core_1). TRACE32 also supports mixed AMP/SMP operation. E.g. MPC5746M can be controlled with two PowerView instances, one for core_2 (IOP) and one controlling core_0 and core_1 in SMP mode. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 39...

  • Page 40: Smp Debugging

    If any of the cores hits a breakpoint, PowerView automatically selects the core that hit the breakpoint. The currently selected core displayed in the status bar and can be changed by right-clicking on the core field. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 40...

  • Page 41: Amp Debugging

    SYStem.CONFIG.SLAVE must be OFF for the core that starts running right form reset. Set to ON for all other cores (that are released later by the first core). SYStem.CONFIG.SLAVE OFF SYStem.CONFIG.SLAVE ON ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 41...

  • Page 42: Watchdog Timer Support

    If it is intended to debug with SWT enabled, please ensure that the application sets the SWT_CR[FRZ] bit when it sets up the SWT. The FRZ bit configures the SWT to automatically halt when the core halts for the debugger. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 42...

  • Page 43: Chip External Watchdog

    Not available NEXUS Adapter MDO8 LA-7630 Pin 27 on Mictor-38 connector (with LA-7631) NEXUS Adapter Pin 28 on 50-pin Samtec connector (with LA-7636) AutoFocus Pin 50 on GlenAir51 connector (with LA-7632) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 43...

  • Page 44: Censorship Unlock

    If the debugger’s reset output is connected to ESR0, SYStem.Up will perform a functional reset and the unlock will succeed. If the debugger’s reset output is connected to PORST, the processor will perform a destructive reset and the unlock during SYStem.Up will fail. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 44...
  • Page 45 BAF code. This method supports debugging/tracing through power cycles. SYStem.CPU <cpu> CORE.ASSIGN <cores> SYStem.Option KEYCODE <password> SYStem.Option ResBreak OFF SYStem.Option WaitReset 0s RESET SYStem.Option ResetMode PIN SYStem.Up ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 45...

  • Page 46: Recovering A Censored Processor (Mpc57Xx, Spc57X/Spc58X And S32R)

    In order to recover a censored processor, first set up the debugger using either method 2, 3 or 4 from above chapter. If the setup is complete, halt the core at power-on reset. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 46...
  • Page 47 It is recommended to find a suitable timing using a good target before trying recovery. The <delay> parameter of SYStem.Option.WaitReset accepts time values in µs resolution. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 47...

  • Page 48: Non-Secure Boot (S32R294)

    Example: SYStem.CPU S32R294 CORE.ASSIGN 1 2 3 SYStem.Option.ResBreak OFF SYStem.Up ;Core is now halted at first instruction of user application ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 48...

  • Page 49: Troubleshooting Debug

    • A JTAG communication error prevented a correct CPU detection. See the message AREA for more information. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 49...
  • Page 50 (e.g. clocks). In this case the message AREA shows the address that caused the problem. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 50...

  • Page 51: Tracing

    NEXUS adapter (LA-7630 or LA-7610) is in use. The on-chip trace license is also not required when the Aurora NEXUS preprocessor (LA-3911) is connected. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 51...
  • Page 52 Onchip Trace Buffer”. The configuration can also be scripted depending on connected processor and debug tool. See Onchip.TBARange for an example. The configuration of trace methods and clients is done through the NEXUS TrOnchip command groups. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 52...

  • Page 53: External Trace Ports (Parallel Nexus/Aurora Nexus)

    Example for MPC5777M SYStem.CPU MPC5777M NEXUS.PortSize 4Lane NEXUS.PortMode 1250Mbps NEXUS.RefClock ON SYStem.Up ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 53...

  • Page 54: Tracing The Program Flow

    With this method, the accuracy of function-level runtime measurements is identical to classical branch trace. Setup of branch history tracing + function call tracing: NEXUS.BTM NEXUS.HTM NEXUS.PTCM.BL_HTM ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 54...

  • Page 55: Tracing Of Data (Read/Write) Transactions

    ID of the currently active process. If the OS Awareness is set up, the address of the memory location can be retrieved using the function TASK.CONFIG(). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 55...

  • Page 56: Trace Context Switch Using Ownership Trace Messaging (Otm)

    One timestamp is generated for each NEXUS trace message. This chapter shows how the timestamps work under several scenarios, implications of using on-chip timestamps and which processors support on-chip timestamps. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 56...

  • Page 57: Trace Based Run-Time Measurement For Off-Chip Parallel Nexus

    Due to the limited amount of buffer size (up to 2MBytes on emulation devices), recording the timestamp information will noticeably reduce the amount of trace events stored in the on-chip trace buffer. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 57...

  • Page 58: Correlation Of The Trace Timestamp With Other Tool Timestamps

    As this processor series does not generate timestamp overflow messages, trace events must be frequent enough so that not more than one timestamp overflow can occur between two events. Assuming a 300MHz core frequency, the 30-bit timestamp will overflow every 3.58 seconds. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 58...

  • Page 59: Processors With On-Chip Timestamp Support

    Watchpoints are set using the command Break.Set, similar to breakpoints that halt the core, but additionally include an option to define the desired behavior: Break.Set <address>|<range> /<action> Define trace filter or trigger ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 59...
  • Page 60 NEXUS module, no watchpoints are used in this case. • Actions on data address (excluding TraceEnable) can not differentiate between read and write access. Only /ReadWrite is allowed. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 60...

  • Page 61: Example: Selective Program Tracing

    Break.Set &a2 /Program /TraceEnable ;run application Trace.Init WAIT 5.s Break ;statistic analysis Trace.STATistic.AddressDURation &a1 &a2 ;plot time distance over time (can take some time for analysis) Trace.PROFILECHART.DURATION /FILTERA ADDRess &a1 /FILTERB ADDRess &a2 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 61...

  • Page 62: Example: Event Controlled Program/Data Trace Start And End

    ;Enable program/data trace only when a specific task is active ;NOTE: RTOS support must be set up correctly &magic=TASK.MAGIC("my_task") ;get magic value for the task of interest Break.Set task.config(magic) /ReadWrite /Data &magic /TraceON Break.Set task.config(magic) /ReadWrite /Data !&magic /TraceOFF ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 62...

  • Page 63: Example: Event Controlled Trace Recording

    PowerProbe or PowerIntegrator, as well as with external tools (using the trigger connector) ;Generate PODBUS trigger signal on data access event with data value Var.Break.Set flags[9] /ReadWrite /Data.Byte 0x01 /BusTrigger ;forward signal to trigger connector TrBus.Connect Out TrBus.Mode High ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 63...

  • Page 64: Example: Event Counter

    The MPC5xxx peripheral bus master trace clients support two freely configurable address ranges. The client will only generate trace messages, if the read or write address is inside one of those address ranges. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 64...

  • Page 65: Trace Filtering And Triggering Features Provided By Trace32

    The command sYmbol.List.ATTRibute opens a window that displays all address ranges of the debug symbols and if the instructions are FLE or VLE. The ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 65...
  • Page 66 ; sYmbol.NEW.ATTRibute <FLE|VLE> <range> ; Example: override Data.LOAD auto project.elf sYmbol.NEW.ATTRibute FLE 0x00000000--0x0003ffff sYmbol.NEW.ATTRibute VLE 0x00040000--0x00ffffff ;add new attribute FLE for BAM, which is not covered by debug symbols sYmbol.NEW.ATTRibute FLE 0xFFFFF000 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 66...

  • Page 67: Flash Programming Support

    / target setup for advanced configuration. No user interaction occurs. PORTSHARING=ON Enable debug port sharing with other tools, e.g. ETAS ETK. If this parameter is passed to the flash script, the flash script calls SYStem.CONFIG PortSHaring ON ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 67...
  • Page 68 DO ~~/demo/powerpc/flash/mpc5676r.cmm PREPAREONLY Data.Set ANC:0xC3F80000 %LONG 0x06000000 ;PLL for fast programming SYStem.BdmClock 20.MHz ;for faster download ;program FLASH FLASH.ReProgram ALL /Erase Data.LOAD.Elf project.x FLASH.ReProgram off ;after flash programming: reset processor SYStem.Up ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 68...

  • Page 69: Requirements Due To Flash Ecc Protection

    • 64-bit units were programmed more than once • problems during programming (e.g. power fail, software issues) • it is a new device, which was never programmed/erased after factory tests ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 69...

  • Page 70: Programming The Rchw Or Boot Header

    In order to enable programming or erasing the shadow row, the flash declaration has to be changed to algorithm TARGET. Example: ;prepare flash programming DO ~~/demo/powerpc/flash/mpc5xxx.cmm PREPAREONLY ;enable shadow row programming (change type NOP to TARGET) FLASH.CHANGETYPE <shadow_row_base>++0x3FF TARGET ;program FLASH FLASH.ReProgram ALL ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 70...
  • Page 71 Every time the shadow row is erased, the debugger will force restore the default censorship word. The next chapter describes how to override this extra protection and change the censorship word in flash. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 71...

  • Page 72: Programming Serial Boot Password And Censorship Word

    Processors with 256-bit passwords do not have that restriction. Newer processors (MPC56XX, SPC56X and later) have a feature to inhibit censorship via JTAG (using the serial password). See SYStem.Option KEYCODE for details. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 72...

  • Page 73: Test / Utest / Otp Flash Programming

    FLASH.ReProgram ALL /Erase Data.LOAD.Elf project.x Data.LOAD.S3 data.s3 FLASH.ReProgram off ;Step 2: Program OTP FLASH.Program 0x00400000--0x00403FFF /OTP Data.LOAD.Binary <file> <start_address> ;and/or alternatively: Data.Set %Quad <address> %Quad <dcf_record1> [<dcf_record2> ...] FLASH.Program off ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 73...

  • Page 74: Programming An Utest Sector Which Is Not Set To Otp

    Programming an UTEST Sector which is not set to OTP The UTEST sector can be either OTP or erasable, depending on factory configuration or custom configuration. Please check the processor reference manual for details. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 74...

  • Page 75: Brownout Depletion Recovery

    In order to investigate such problems, use the following commands to find out which address ranges are contained in the loaded file. ; find out which addresses are contained in loaded file Data.LOAD.auto * /VM sYmbol.List.Map ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 75...
  • Page 76 FLASH.Erase only as fallback instead of adding it to the start of every new Flash.ReProgram cycle. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 76...

  • Page 77: Command Reference: System Commands

    Please make sure to decrease the JTAG frequency to 1/4th of the reset core frequency before a target reset (e.g. SYStem.Up). See processor data sheet for additional restrictions of the max. JTAG frequency. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 77...

  • Page 78: System.config.state

    Lets you configure the XCP connection to your target. For descriptions of the commands on the XCP tab, see “XCP Debug Back-End” (backend_xcp.pdf). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 78...

  • Page 79: System.config

    When using the TriState mode, nTRST/JCOMP must have a pull-up resistor on the target. In TriState mode, a pull-down is recommended for TCK, but targets with pull- up are also supported. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 79...
  • Page 80 TDI signal and the core of interest. This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 80...
  • Page 81 CJTAGTCA <value> Selects the TCA (TAP Controller Address) to address a device in a cJTAG Star-2 configuration. The Star-2 configuration requires a unique TCA for each device on the debug port. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 81...
  • Page 82 SYStem.CONFIG DRPOST ; DRPOST: Add up one DR bit per TAP which ; is in BYPASS mode, i.e. 1. + 1. + 1. = 3. ; This completes the configuration. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 82...
  • Page 83 TapStates Exit2-DR Exit1-DR Shift-DR Pause-DR Select-IR-Scan Update-DR Capture-DR Select-DR-Scan Exit2-IR Exit1-IR Shift-IR Pause-IR Run-Test/Idle Update-IR Capture-IR Test-Logic-Reset ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 83...

  • Page 84: System.config.debugporttype Set Debug Cable Interface Mode

    06/2009...12/2012: restricted support (TDI and TDO signal of Nexus adapter must be disconnected from any target signal when using cJTAG) 05/2009 and older: not supported • LA-7610 (Nexus adapter 3.3V): not supported • LA-7612 (Nexus adapter 5V): not supported ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 84...

  • Page 85: System.config.extwdtdis

    (not XCP) LowwhenStopped The WDTDIS pin is driven low when program is stopped. (not XCP) Trigger The WDTDIS pin is driven by the Complex Trigger Unit. (only parallel NEXUS Adapter) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 85...

  • Page 86: System.config Portsharing

    In the case the processor is not listed and not detected by SYStem.DETECT CPU, check if an updated version of TRACE32 is available (http://www.lauterbach.com/3232) or contact technical support. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 86...

  • Page 87: System.lock

    MPC57XX/SPC57X/SPC58X: Data cache is write-through, so reading cached data is always possible, updating cached contents also is supported on most of these processors. MPC5777C: See SYStem.Option NexusMemoryCoherency ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 87...
  • Page 88 (e.g. in terms of cache coherency) my differ depending on the XCP slave hardware, firmware or configuration. • These processors do not support run-time memory access via NEXUS: NOTE: MPC5601D, MPC5602D, MPC5601P, MPC5602P ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 88...

  • Page 89: System.mode

    CPU at the first instruction, place a temporary on-chip breakpoint range (Break 0--0xFFFFFFFC /Onchip) Resets the target/processor and sets the CPU to debug mode. After execution of this command the CPU is stopped and prepared for debugging. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 89...

  • Page 90: Command Reference: System.option Commands

    Default: ON. This command configures how the debugger will maintain cache coherence for the debugger’s memory accesses while the core is halted in debug mode. The setting has no impact on the run-time memory access. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 90...

  • Page 91: System.option Dcread

    OFF. Please note that debugger-generated resets (e.g. SYStem.Up) also contribute to the number of resets that trigger the reset escalation. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 91...

  • Page 92: System.option Disableshortsequence

    OFF, you have to turn it ON again and perform another SYStem.Up. SYStem.Option DisMode Disassembler operation mode Format: SYStem.Option DisMode <mode> <mode>: ACCESS AUTO MPC5XXX/SPC5XX with VLE instruction set support only. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 92...

  • Page 93: System.option Dualport

    Only physical addresses accesses are possible. Use the access class modifier “A:” to declare the access physical addressed, or declare the address translation in the debugger-based MMU manually using TRANSlation.Create. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 93...

  • Page 94: System.option Fastaccess Special Operation Mode For Fast Run Control

    FREEZE bit. For details please see the processor reference manual. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 94...

  • Page 95: System.option Holdreset

    P: (program memory) display the memory values from the instruction/unified cache if valid. If the data is not available in cache, the physical memory will be displayed. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 95...

  • Page 96: System.option Imaskasm

    Use this command to inhibit the censorship protection. The processor will then be unlocked during the next start of the debug session (SYStem.Up, SYStem.Mode.Attach, SYStem.Mode.StandBy etc.). (no password) Calling SYStem.Option KEYCODE without parameters disables the censorship inhibit feature. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 96...
  • Page 97 Devices with C90LC Flash require the upper and lower DWORD exchanged when specified as parameter of SYStem.Option KEYCODE. • MPC577xK (RaceRunner) only: If no password is set, the debugger automatically unlocks the processor using the public password (0xDEADDEEDFADEBADE) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 97...

  • Page 98: System.option Lpmdebug

    HANDSHAKE TRACE32 uses LPM handshake for low power mode debugging. The processor signals LPM entries and exits to the debugger. At LPM exit breakpoints and NEXUS settings are re-established. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 98...

  • Page 99: System.option Lockstepdebug

    (MPC57XX/SPC57X/SPC58X). SYStem.Option MMUSPACES Separate address spaces by space IDs Format: SYStem.Option MMUSPACES [ON | OFF] SYStem.Option MMUspaces [ON | OFF] (deprecated) SYStem.Option MMU [ON | OFF] (deprecated) Default: OFF. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 99...

  • Page 100: System.option Nexusmemorycoherency

    It is essential to set this option to ON only if the data cache is configured to write-through mode (L1CSR0[DCWM]==1). If the cache is operated in copy-back mode, setting this option to ON can cause undefined behavior. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 100...

  • Page 101: System.option Nodebugstop

    JTAG_RDY signal, the JTAG_RDY pin of the debug connected should be connected to GND. If the JTAG_RDY pin is left unconnected, use SYStem.Option NOJTAGRDY ON to prevent problems with probing this signal. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 101...

  • Page 102: System.option Notrap

    If ON, TRAP instruction is not treated as debug event. The Debugger always uses the DNH instruction for software breakpoints regardless of this setting. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 102...

  • Page 103: System.option Overlay

    When setting a fetch address, make sure that the address does not cause an instruction storage exception, e.g. because of unimplemented memory or ECC errors (e.g. in FLASH or uninitialized SRAM). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 103...

  • Page 104: System.option Resetbehavior

    Once the core is out of reset, the debugger sets debug and trace configuration registers on-the-fly. SYStem.Option ResBreak Halt the core while reset asserted Format: SYStem.Option ResBreak [ON | OFF] Default: ON. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 104...

  • Page 105: System.option Resetdetection

    Processors which require the PCRs to be configured by the debugger for tracing, reset detection has to be enabled in order to enable tracing through reset. <method> Function Reset detection is disabled. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 105...

  • Page 106: System.option Resetmode

    The reset pin of the debug/trace connector is asserted as well. FUNCtional The debugger performs a functional reset using the DCI module. The reset pin of the debug/trace connector is not asserted. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 106...

  • Page 107: System.option Slowreset

    If the address range of the interrupt vectors are specified by this command, the TRACE32 NEXUS debugger marks all indirect branches to these addresses / the address range as interrupt. This information is needed for correct trace display and run-time statistic analysis. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 107...
  • Page 108 IVPR/IVOR &startaddr=R(IVPR) registers &range=DATA.LONG(SPR:415.) SYStem.Option VECTORS &startaddr++&range ;IVPR/IVOR must already be initialized ;&range = MAX(IVOR0..IVOR34) use debug symbols SYStem.Option VECTORS IVOR0_func IVOR1_func … use debug symbol SYStem.Option VECTORS IVOR0_fnc--(IVOR15_fnc+3) range ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 108...

  • Page 109: System.option Waitreset

    RESET pin RESET/BIST RESET DEBUG_HALT CPU State For related commands, see also SYStem.Option HoldReset SYStem.Option SLOWRESET. See chapter Censorship Unlock for typical use cases of this command. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 109...

  • Page 110: System.option Watchdog

    MPC56XX, SPC56X, MPC57XX, SPC57X: CR[WEN] CR[FRZ] CR[HLK] Debugger Action CR[SLK] don’t care don’t care none don’t care none SLK on set FRZ HLK off HLK on service watchdog (see note) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 110...
  • Page 111 If the system option is ON, the debugger will configure the watchdog to the longest timeout period on SYStem.Up and SYStem.Mode.StandBy. During debugging, the watchdog timer will be serviced if SWE is on. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 111...

  • Page 112: Command Reference: Mmu Commands

    <range> or <address> have a space ID: displays the translation table of the specified process • else, this command displays the table the CPU currently uses for MMU translation. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 112...
  • Page 113 • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 113...

  • Page 114: Mmu.list

    <range> or <address> have a space ID: list the translation table of the specified process • else, this command lists the table the CPU currently uses for MMU translation. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 114...
  • Page 115 • For information about the first three parameters, see “What to know about the Task Parameters” (general_ref_t.pdf). • See also the appropriate OS Awareness Manuals. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 115...

  • Page 116: Mmu.scan

    This command reads the OS kernel MMU table and the MMU tables of all processes and copies the complete address translation into the debugger- internal static translation table. See also the appropriate OS Awareness Manual. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 116...

  • Page 117: Mmu.set

    TLB (or MPU) entry. See the processor’s <mas2> reference manual for details on MAS registers. <mas3> For processors with a core MPU (MPC57XX/SPC57X series), use TLB2 to generate an MPU entry). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 117...

  • Page 118: Command Reference: Benchmarkcounter

    Enables event triggered counter start/stop. The events are defines using ALPHA and BETA breakpoints set with Break.Set. Every time the Alpha breakpoint condition triggers, the counter is started. The counter stops when the Beta breakpoint condition is triggered. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 118...
  • Page 119 ;set up CNT0 to count processor cycles (using start/stop event) BMC.CNT0.EVENT PROC-CYC BMC.CNT0.ATOB ON ;set up CNT2 to count function entries BMC.CNT2.EVENT ALPHA ;run measurement (for 10 seconds) BMC.Init Wait 10s Break PRINT FORMAT.DECIMAL(1.,BMC.COUNTER(0)/BMC.COUNTER(2))+" cycles" ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 119...
  • Page 120 ;set up CNT0 to count processor cycles (using start/stop event) BMC.CNT0.EVENT PROC-CYC BMC.CNT0.ATOB ON ;set up CNT2 to count function entries BMC.CNT2.EVENT CHARLY ;run measurement (for 10 seconds) BMC.Init Wait 10s Break PRINT FORMAT.DECIMAL(1.,BMC.COUNTER(0)/BMC.COUNTER(2))+" cycles" ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 120...

  • Page 121: Bmc..Freeze Freeze Counter In Certain Core States

    If contradicting states are enabled (e.g. SUPERVISOR and USER), the counter will be permanently frozen. The table below explains the meaning of the individual states. <state> Dependency in core USER Counter frozen if MSR[PR]==1 SUPERVISOR Counter frozen if MSR[PR]==0 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 121...

  • Page 122: Bmc.freeze

    Freeze counters while core halted Format: BMC.FREEZE [ON | OFF] On MPC5XXX, the core performance counters automatically stop when a core enters debug mode. Therefore this command has no effect. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 122...

  • Page 123: Command Reference: Tronchip

    An error message is displayed when the user wants to set a new data address breakpoint after all on-chip breakpoints are spent by a data address breakpoint to an address range. TrOnchip.CONVert ON Break.Set 0x6020++0x1f Break.Set 0x7400++0x3f Data.View 0x6020 Data.View 0x7400 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 123...

  • Page 124: Tronchip.edbrac0

    The selected events are excluded from debugger use (via Break.Set) and are available for direct register configuration through debugger writes, e.g. Data.Set. See core reference manual for the EDBRAC0/DBERC0 bit definitions. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 124...

  • Page 125: Tronchip.evten

    LA-7610 and LA-7612 only: If the EVTx pins are not used for EVTI/EVTO, they must not be connected to the debug/trace connector. • LA-7630: EVTI pin is tristated when TrOnchip.EVTEN is OFF. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 125...

  • Page 126: Tronchip.reset

    BKPT Execution of the BKPT pseudo-opcode. (Default: ON) Please note that this opcode represents the software breakpoint for e200z750, e200z6, e200z3, e200z1 and e200z0Hn2 cores when operated in VLE mode. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 126...

  • Page 127: Tronchip.varconvert

    + Requires only one single address breakpoint. - Program will not stop on unintentional accesses to the variable’s address space. TrOnchip.VarCONVert ON Var.Break.Set vint /Write Data.View vint TrOnchip.VarCONVert OFF Var.Break.Set vint /Write Data.View vint ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 127...

  • Page 128: Tronchip.state

    Displays the TrOnchip.state window for on-chip trigger setup. Different commands are available in the TrOnchip.state window, depending on the Lauterbach hardware used: NEXUS adapter LA-7610/12/30 Debug cable LA-2708, LA-3736 (AUTO26) pinout) Debug cable LA-7753 (JTAG/OnCE pinout) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 128...

  • Page 129: Command Reference: Onchip

    &all NEXUS.RefClock ON &all Trace.Method Analyzer ELSE ;use on-chip trace buffer of buddy die Onchip.TBARange EEC:0x0C000000--0x0C1FFFFF &all Trace.Method Onchip ELSE ;use on-chip trace buffer of production device Onchip.TBARange A:0x0D000000--0x0D003FFF &all Trace.Method Onchip ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 129...

  • Page 130: Command Reference: Nexus

    NEXUS.CLIENT2.MODE [Read | Write | ReadWrite | OFF] NEXUS.CLIENT3.MODE [Read | Write | ReadWrite | OFF] Sets the data trace mode of the selected trace client. Select the trace client using NEXUS.CLIENT<x>.SELECT before setting the trace mode. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 130...

  • Page 131: Nexus.client.Select

    TRACE32 state line shows you the list of logical cores that form the SMP system. NEXUS.CoreENable 1. ; Enable core tracing only for ; the logical core 1. of the SMP ; system ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 131...

  • Page 132: Nexus.ddr

    (Analyzer.SAMPLE) NEXUS.DMADTM Enable DMA data trace messaging Format: NEXUS.DMADTM [Read | Write | ReadWrite | DTM | OFF] (deprecated) SYStem.Option DMADTM [ON | OFF] (deprecated) Deprecated. Use NEXUS.CLIENT<x> commands. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 132...

  • Page 133: Nexus.dtm

    IEEE-ISTO 5001-2008 or later. Ignore MSR[PMM] for masking data trace messages (default) Mask (disable) data trace messages when MSR[PMM] = 0, unmask (enable) data trace messages when MSR[PMM] = 1 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 133...

  • Page 134: Nexus.dtmwhilehalted

    ISTO 5001-2008 or later. NEXUS.FRAYDTM Enable FlexRay data trace messaging Format: NEXUS.FRAYDTM [Read | Write | ReadWrite | DTM | OFF] (deprecated) SYStem.Option DMADTM [ON | OFF] (deprecated) Deprecated. Use NEXUS.CLIENT<x> commands. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 134...

  • Page 135: Nexus.htm

    (e.g. XETK-V2 in data trace configuration). The debugger will continue to record the trace as a slave (i.e. trace configuration is exclusively done by calibration tool). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 135...

  • Page 136: Nexus.on Switch The Nexus Trace Port On

    The NEXUS trace port is switched on. All trace registers are configured by debugger. Do not use if calibration tool makes use of data trace (e.g. XETK-V2 in data trace configuration). ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 136...

  • Page 137: Nexus.otm

    NEXUS.PCRCONFIG [ON | OFF] When enabled, the debugger configures the pads of MCKO, MDO and MSEO to NEXUS function. This command is only implemented for MPC560xS / SPC560S (Spectrum) and SPC56AP60. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 137...

  • Page 138: Nexus.pincr

    Parallel NEXUS: Please check in the processor’s data sheet if the NEXUS trace port of your processor is functional at the selected system frequency and MCKO divider. Current silicon versions allow trace port frequencies up to 60~80 MHz. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 138...

  • Page 139: Nexus.portsize

    Enable this option, when the OTM is used to generate trace information about task switches. OTMs are usually used for task switch tracing on processors with NEXUS 2+, because data trace is unavailable. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 139...

  • Page 140: Nexus.ptcm

    IEEE-ISTO 5001-2008 or later. Ignore MSR[PMM] for masking program trace messages (default) Mask (disable) program trace messages when MSR[PMM] = 0, unmask (enable) program trace messages when MSR[PMM] = 1 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 140...

  • Page 141: Nexus.refclock

    Enable workaround for doubly issued register full messages. The program flow decoder will ignore the duplicate message when the processor sends the message twice within the specified time. Affected processors are: MPC564xB/C, SPC564B/SPC56EC, MPC5674F, MPC567xK, SPC57HK, MPC564xL, SPC56EL, MPC564xA, SPC564A. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 141...

  • Page 142: Nexus.smarttrace

    For processors which implement the IEEE-ISTO 5001-2008 or later, STALL can be configured to occur at several fill levels, while processors which implement an older standard have a fixed level. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 142...

  • Page 143: Nexus.state

    Not all trace clients of a processor may support NEXUS timestamps. (e.g. MPC5746M and SPC57EM80 do not support timestamps for NEXUS messages of the cores) • Timestamps will consume ~20% of the trace bandwidth/trace memory ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 143...

  • Page 144: Nexus.wtm

    NEXUS outputs watchpoint messages. No watchpoint messages are output by NEXUS. NOTE: When a watchpoint is set with a Break.Set command, the NEXUS.WTM setting will be internally overridden to ON. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 144...

  • Page 145: Nexus Specific Tronchip Commands

    For a description of the functionality and examples, see Trace Filtering and Triggering with Debug Events Tracing Peripheral Modules / Bus Masters. TrOnchip.Beta Set special breakpoint function Format: TrOnchip.Beta <function> See TrOnchip.Alpha. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 145...

  • Page 146: Tronchip.charly

    The NEXUS memory access is not affected by this command. To re-enable NEXUS register control, use command TrOnchip.ENable. Per default, NEXUS register control is enabled. TrOnchip.Echo Set special breakpoint function Format: TrOnchip.Echo <function> See TrOnchip.Alpha. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 146...

  • Page 147: Tronchip.enable

    • Only enable this option if the EVTO pin of the processor is connected to NOTE: the NEXUS connector. • This option has no effect if TrOnchip.EVTEN is disabled. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 147...

  • Page 148: Tronchip.external

    WDTC source can be used to activate the OUT0 output in parallel to the TD/WDTE pin. It can control an external WDTC (or something else). It is a second output, controlled by TrOnchip.TOOLIO2. ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 148...

  • Page 149: Tronchip.out1

    Selects the signal source for the OUT1 pin of the NEXUS connector. Only available on LA-7610. Trigger Trigger output of CTU (OUT.B) Permanently low (GND) High Permanently high (VCC) Low while CPU running, high while stopped ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 149...

  • Page 150: Tronchip.toolio2

    Permanently low (GND) High Permanently high (VCC) Low while CPU running, high while stopped; can be used to disable on- board watchdogs. Stop High while CPU running, low while stopped ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 150...

  • Page 151: Tronchip.tracecontrol

    The example below shows how to disable the program trace for interrupts. On account of the on-chip implementation, the program trace will start after the first interrupt return (RFI instruction) is executed. ;Disable program trace for interrupt handler TrOnchip.TRaceControl IRPT TraceOFF TrOnchip.TRaceControl RET TraceON ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 151...

  • Page 152: Debug And Trace Connectors

    This connector is compatible to the JTAG connector used on the NXP/Freescale and STM evaluation boards. AUTO26 Connector (JTAG) Signal Signal VTREF KEY(GND) GND(PRESENCE) RESET- RESETOUT- WDTDIS JCOMP EVTI- EVTO- BREQ- BGRNT- EXTIO ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 152...

  • Page 153: 10-Pin Ecu14 Connector (With Converter La-3843)

    MDO12 MDO13 MDO14 MDO15 MDO09 (CLKOUT) MDO08 RSTIN- EVTI- VTREF MDO10 RDY- MDO07 MDO06 MDO05 JCOMP MDO04 MDO11 MDO03 RESETOUT MDO02 TDET/WDTDIS MDO01 BGRNT MDO00 EVTO- MCKO BREQ MSEO1- MSEO0- ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 153...

  • Page 154: 50-Pin Samtec Erf8 Connector (Nexus Parallel)

    MDO01 TRST- (JCOMP) MDO02 DBGACK- (RDY) MDO03 EVTI- EVTO- MCKO RSTIN- MDO04 RSTOUT MDO05 CLKOUT MDO06 TD/WDTE MDO07 DAI1 MDO08 DAI2 MDO09 ARBREQ MDO10 ARBGRT MDO11 MDO13 MDO12 MDO14 MDO15 ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 154...

  • Page 155: 51-Pin Glenair / Robust Connector (Nexus Parallel)

    51-pin GlenAir / ROBUST Connector (NEXUS parallel) Signal ARBREQ(TOOLIO0) RDY- RSTIN- VREF EVTI- TRST- MDO0 MCKO EVTO- MSEO0- MDO9 MDO1 MDO2 MDO3 ARBGRT(TOOLIO1) MSEO1- MDO4 MDO5 MDO6 MDO7 MDO8 MDO10 MDO11 GND (TDET) RSTOUT(VENIO2) ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 155...

  • Page 156: 34-Pin Samtec Erf8 Connector (Aurora Nexus)

    34-pin SAMTEC ERF8 Connector (Aurora NEXUS) Signal Signal TXP0 JTAG-VTREF TXN0 TXP1 TXN1 JCOMP- TXP2 TXN2 EVTI- EVTO- TXP3 RSTOUT- TXN3 RSTIN- CLKP CLKN RDY- WDIS ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 156...

  • Page 157: Mechanical Dimensions

    SIDE VIEW ALL DIMENSIONS IN 1/1000 INCH CONVERTER MICTOR TO GLENAIR 51 TOP VIEW PIN1 PIN1 INSIDE OUTSIDE TWO ROTATE VERSIONS OF THE GLENAIR 51 PLUG AVAILABLE STANDARD ORIENTATION IS OUTSIDE ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 157...
  • Page 158 OUTSIDE TWO ROTATE VERSIONS OF THE GLENAIR 51 PLUG AVAILABLE STANDARD ORIENTATION IS OUTSIDE LA-7612 NEXUS-MPC551X TOP VIEW CABLE PIN1 1050 1500 4050 SIDE VIEW ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 158...
  • Page 159 Dimension LA-7630 NEXUS-MPC5500-AF TOP VIEW CABLE PIN1 1400 3950 SIDE VIEW ALL DIMENSIONS IN 1/1000 INCH LA-7631 CONV-MIC38-GENERIC TOP VIEW ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 159...
  • Page 160 ALL DIMENSIONS IN 1/1000 INCH LA-7633 CONV-MIC38-MPC5500R 2x dia 100 for screws TOP VIEW LAUTERBACH J101 J103 J100 J102 PIN 1 NAF MODULE ADAPTER MPC55xx ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 160...
  • Page 161 TD WDT DAI1 NEXUS AutoFocus PIN1 ALL DIMENSIONS IN 1/1000 INCH LA-7637 CONV-MIC76-MPC5500-S TOP VIEW TD WDT NEXUS AutoFocus PIN 1 Adapter SAMTEC ERx8 (20 PIN) ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 161...
  • Page 162 Dimension LA-7638 CONV-MIC38-MPC5500-L TOP VIEW PIN1 LAUTERBACH ALL DIMENSIONS IN 1/1000 INCH LA-7639 CONV-MIC38-MPC5500-S TOP VIEW ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 162...
  • Page 163 TOP VIEW 1675 SIDE VIEW 3550 CABLE ( FLEX) ALL DIMENSIONS IN 1/1000 INCH LA-7641 CONV-SAM50-MPC5500-L TOP VIEW 2X diameter 100 for screws PIN1 SIDE VIEW ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 163...
  • Page 164 Dimension LA-7645 NEXUS-AVR32-AF TOP VIEW CABLE PIN1 1400 3950 SIDE VIEW ALL DIMENSIONS IN 1/1000 INCH LA-3725 CONV-MIC38-J14-5500 1000 MICTOR38 PIN1 PIN1 JTAG14 ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 164...
  • Page 165 TO-1325 10.2mm TARGET SOCKET TO-1388 ALL DIMENSIONS IN mm LA-3855 ET176-MPC5607BC TOP VIEW 3150 PIN1 SIDE VIEW 3150 NEXUS connector TET ADAPTER TET SOCKET TARGET ALL DIMENSIONS IN 1/1000 INCH ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 165...

  • Page 166: Technical Data

    0 .. 100MHz Aurora NEXUS: • up to 3.125 gigabit/second with 4 lanes • up to 6.250 gigabit/second with up to 3 lanes • reference clock output up to 3.125 GHz ©1989-2021 Lauterbach GmbH Qorivva MPC5xxx/SPC5xx Debugger and NEXUS Trace 166...

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Spc5 series

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