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micro-line C6713CPU
Orsys micro-line C6713CPU Manuals
Manuals and User Guides for Orsys micro-line C6713CPU. We have
1
Orsys micro-line C6713CPU manual available for free PDF download: Hardware Reference Manual
Orsys micro-line C6713CPU Hardware Reference Manual (54 pages)
High performance DSP / FPGA board
Brand:
Orsys
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
2
1 Preface
6
Document Organization
6
Documentation Overview
6
Notational Conventions
6
Trademarks
7
Revision History
8
2 Hardware Overview
9
Block Diagram of the C6713CPU
10
Figure 1: Block Diagram of the C6713CPU
10
Figure 2: Top Side of the C6713CPU
11
Figure 3: Bottom Side of the C6713CPU
11
Connectors
12
Micro-Line Connectors
12
JTAG Connector
12
Interfaces and Hardware Components
12
Fpga
12
External Memory (On-Board SDRAM)
13
Figure 4: FPGA Connections Overview
13
Flash Memory
14
Pld
14
UART / RS-232 Interface
14
Temperature Sensor
14
Reset Generator and Watchdog
15
External Flags (XF Signals)
15
Power Supply of the Board
15
Status Led's
15
Micro Line C6713Cpu
15
User Programmable Led's (PLD)
16
User Programmable LED (FPGA)
16
DSP Peripherals
16
Multichannel Audio Serial Ports (Mcasp)
16
External Memory Interface (EMIF)
16
Inter Integrated Circuit
17
Interfaces
17
General Purpose Input / Output Pins (GPIO)
17
Multi-Channel Buffered Serial Ports (Mcbsp)
17
Timers
18
Host Port Interface (HPI)
18
Interrupts
18
Dma
19
3 Memory Maps and Description of the Pld Registers
20
TMS320C6713 Memory Map
20
Date : 28 November
20
Table 1: Memory Map of the Processor
20
C6713CPU Address Map
21
Internal Fast SRAM
21
DSP Peripherals
21
External SDRAM
21
Flash Memory
21
Table 2: Memory Map of the C6713CPU
21
Endianness
22
Figure 5: Data Representation in Memory in Little Endian Configuration
22
EMIF Configuration
23
Default EMIF Configuration
23
Description of the PLD Board Registers
23
Table 3: Default Initialization Values for the FPGA Related CE Space Registers
23
Table 4: CE2 Default Configuration
23
Table 5: CE3 Default Configuration
23
Description of the PLD Registers
24
Hardware Configuration Register (HWCFG)
24
Table 6: PLD and UART Registers of the C6713CPU
24
Table 7: PLD Register Quick Reference
24
FPGA Control Register (FCR)
25
LED Control Register (LED)
25
Module Control Register (MCR)
26
I 2 C Bus Control Register (I2C)
26
External Flag Register (XF)
27
Watchdog Register (WDG)
27
Version Register (VER)
28
Table 8: Version Register Encoding
28
4 Boot Process and Default Setup of the C6713Cpu
29
Table 9: Default Clock and EMIF Settings of the C6713CPU
29
5 Using the Flash File System
30
6 Description of the Micro-Line
31
Board Connectors
31
Location of the Connectors
31
Figure 6: Connector Locations
31
Connector Overview
32
Pinout Tables of the Micro-Line
32
Connector
32
Table 10: Connector Overview
32
Table 11: Pinout of the Micro-Line ® Connectors
32
Table 12: Pinout Summary for the Mcbsp Interfaces
33
Table 13: Pinout Summary for the Timers
33
C Interfaces
33
Table 15: Pinout Summary and Signal Routing for the Mcasp Interfaces
34
Pinout of the JTAG Connector
35
Table 16: Pinout of the JTAG Connector
35
Figure 7: JTAG Adapter for the C6713CPU
35
Function of the Micro-Line Connector Pins
36
Connector a
36
Connector B
36
Connector BB
36
Connector D
37
Connector E
38
7 Environment
44
Minimum Connections
44
Figure 8: Supplying the C6713CPU with Power
44
Figure 9: Connecting the Serial Interface (RS-232) to a PC
45
Changing the Board Configuration
46
Location of Modifiable Components
46
Table 17: Factory Default Configuration Summary
46
Figure 10: Location of Configuration Elements (Top Side)
46
Configuring DSP Clock Speed
47
Date : 28 November
47
Configuring for HPI or Mcasp1 Usage
47
Configuring Micro-Line ® Pin D30 Termination
47
Configuring for I 2 C Interface #0 Operation
47
Figure 11: Location of Configuration Elements (Bottom Side)
47
Configuring CLKS1 / SCL1 Termination
48
Configuring FPGA I/O Behavior When FPGA Is Not Loaded
48
Signal Levels and Loads
48
Input Voltage Levels for Non-FPGA Signals
48
Output Voltage Levels for Non-FPGA Signals
48
Allowed Output Loads
48
Supply Voltage
49
Power Consumption
49
Reset Timing
49
Ambient Temperature
49
Ambient Humidity
49
Table 18: Voltage Limits for the C6713CPU
49
Table 19: Power Consumption of the C6713CPU
49
Table 20: Reset Timing
49
Dimensions of the Board
50
Figure 12: Dimensions of the C6713CPU (in Millimeters)
50
Figure 13: Complete Micro-Line ® Footprint
51
Spare Micro-Line Connectors
52
Figure 14: C6713CPU Connector Pins
52
8 List of Abbreviations Used in this Document
53
9 Literature References
54
Reference ® C6713Cpu
54
Date : 28 November
54
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