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Summary of Contents for Orsys micro-line C6713CPU
- Page 1 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE Iss./Rev : 1.1 Page Hardware Reference Guide ® micro-line C6713CPU High performance DSP / FPGA board Orsys Orth System GmbH, Am Stadtgraben 25, 88677 Markdorf Germany http://www.orsys.de...
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Page 2: Table Of Contents
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page Contents 1 PREFACE........................6 Document Organization ......................6 Documentation Overview ...................... 6 Notational conventions......................6 Trademarks ..........................7 Revision History ........................8 2 HARDWARE OVERVIEW ..................... - Page 3 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page Internal fast SRAM ....................... 21 DSP Peripherals ........................21 External SDRAM ........................21 Flash Memory ........................21 Endianness ........................... 22 EMIF Configuration ......................
- Page 4 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page 7.2.3 Configuring for HPI or McASP1 Usage ................47 ® 7.2.4 Configuring micro-line Pin D30 Termination ..............47 7.2.5 Configuring for I C interface #0 Operation ................
- Page 5 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page List of Tables Table 1: Memory map of the processor................... 20 Table 2: Memory map of the C6713CPU ..................21 Table 3: default initialization values for the FPGA related CE space registers .......
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Page 6: Preface
Chapter 8 explains the abbreviations that are used throughout this document 1.2 Documentation Overview This chapter lists the documentation from ORSYS that is shipped together with the C6713CPU. Further documents from other vendors may also be listed in chapter 9 and are referenced throughout this document in square brackets. -
Page 7: Trademarks
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page Configuration parameters, function names, path names and file names are written in italic typeface. Example: dev_id Source code examples are given in a small, fixed-width typeface. Example: int a = 10;... -
Page 8: Revision History
LINE Page 1.5 Revision History Revision Changes ORSYS internal preliminary version / April 2005 First public preliminary version / May 2005 Completely revised. Block diagram completed. Flash File System: short description only, reference to separate user's guide. Mentioned that HPI usage requires FPGA. -
Page 9: Hardware Overview
(BSP). The FPGA of the C6713CPU can be used either with the default BSP from ORSYS which is pre- installed when the C6713CPU is shipped, or with individual custom designs using the FPGA development option. -
Page 10: Block Diagram Of The C6713Cpu
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 10 2.1 Block Diagram of the C6713CPU Figure 1: Block diagram of the C6713CPU... -
Page 11: Figure 2: Top Side Of The C6713Cpu
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 11 flash memory FPGA green LED (PLD) red LED (PLD) yellow LED (FPGA) JTAG connector micro-line connectors temperature SDRAM sensor Figure 2: Top side of the C6713CPU 16 bit HPI data bus transceiver... -
Page 12: Connectors
Alternatively the FPGA can be individually programmed by the user. This is possible by using an optional FPGA development package from ORSYS together with standard FPGA development tools from Xilinx. FPGA technology allows flexible internal logic and individual I/O... -
Page 13: External Memory (On-Board Sdram)
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 13 ® interfacing over for the majority of the micro-line connector pins. The user is no longer restricted to a fixed I/O logic. The FPGA has access to the following signal groups: •... -
Page 14: Flash Memory
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 14 can be software reconfigured by PLL settings. It can also be generated by the FPGA, allowing any clock frequency up to 100 MHz. Compared to the internal fast SRAM of the DSP chip, the on-board SDRAM is significantly slower. -
Page 15: Reset Generator And Watchdog
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 15 DSP-internal temperature is roughly 15 degrees Celsius above the temperature measured by the sensor. Software drivers for the temperature sensor are included in the development kits, see [20] for details. -
Page 16: User Programmable Led's (Pld)
By default, the McASP1 port is disabled by hardware and the Host Port Interface (HPI) is enabled therefore. If McASP1 is needed for a certain application, a slight hardware reconfiguration on the C6713CPU board is necessary. In this case please contact ORSYS. Further details about McASP1 configuration are also described in chapter 7.2. -
Page 17: Inter Integrated Circuit
C interface #1 of the TMS320C6713 DSP. If the I C interface #0 is also needed for a certain application, a slight hardware reconfiguration of the C6713CPU board is necessary. In this case please contact ORSYS. 2.5.4 General Purpose Input / Output Pins (GPIO) At the TMS320C6713 DSP a couple of GPIO pins are shared with the Host Port Interface (HPI). -
Page 18: Timers
• GPIO HPI booting is not supported by default. If HPI booting is required, please contact ORSYS. HPI operation requires an appropriate FPGA to be loaded, such as [21]. Further information about the HPI can be found in [4] and [6]. HPI operation is enabled in default hardware configuration. -
Page 19: Dma
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 19 2.5.9 DMA The TMS320C6713 DSP provides an enhanced DMA (EDMA) controller with 16 channels and 16 possible synchronization events. It can be used to transfer data between two locations anywhere in the address range of the C6713CPU. -
Page 20: Memory Maps And Description Of The Pld Registers
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 20 3 Memory Maps and Description of the PLD Registers 3.1 TMS320C6713 Memory Map The memory map of the TMS320C6713 is divided into several sections: •... -
Page 21: C6713Cpu Address Map
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 21 3.2 C6713CPU Address Map The table below shows how the C6713CPU uses the four CE address spaces of the processor: address range (hex) CE space size (bytes) Description... -
Page 22: Endianness
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 22 3.7 Endianness When data is transferred between the C6713CPU board and external hardware over the micro- ® line connector it is important to know how data is stored in memory. -
Page 23: Emif Configuration
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 23 3.8 EMIF Configuration All accesses to off-DSP-chip peripherals, such as on-board SDRAM, the UART or the FPGA are performed by the DSP's external memory interface (EMIF). -
Page 24: Description Of The Pld Registers
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 24 base address register name register mnemonic 9010 0000h Hardware configuration register HWCFG 9011 0000h FPGA control register 9012 0000h LED control register 9013 0000h Module control register... -
Page 25: Fpga Control Register (Fcr)
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 25 CPUSPEED: This bit can be used by application software to determine the DSP speed version and to program the DSP's PLL accordingly. -
Page 26: Module Control Register (Mcr)
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 26 RED_LED GREEN_LED RESERVED r, w, 00 r, w, 11 RED_LED: RED_LED Encoding others reserved GREEN_LED: RED_LED Encoding on when CE1 active, that is when Flash, PLD or FPG registers are accessed on when Flash is accessed 3.10.4 Module Control Register (MCR) SW_RESET... -
Page 27: External Flag Register (Xf)
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 27 SDA_STAT SDA_CTL SCL_STAT SCL_CTL RESERVED r, 1 r, w, 1 r, 1 r, w, 1 SDA_STAT: retrieves the current state of the SDA line. If this bit is read as 1, the SDA line is in a logic high state and no device pulls the line low. -
Page 28: Version Register (Ver)
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 28 WDG_RST: The WD_RST pin of the PLD is connected to the watchdog input of the reset generator. If the watchdog is enabled the WD_RST pin must be set to 1 at least once per second. -
Page 29: Boot Process And Default Setup Of The C6713Cpu
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 29 4 Boot Process and Default Setup of the C6713CPU After reset or power up the C6713CPU boots the Flash File System from flash memory. The Flash File System first checks, if a command from a host PC on the RS-232 interface is pending. -
Page 30: Using The Flash File System
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 30 5 Using the Flash File System The Flash File System of the C6713CPU consists of three parts: • A target-resident boot loader which initializes the C6713CPU at startup, looks for commands on the RS-232 interface and then either loads auto-boot FPGA(s) / application or loads a Flash File System command executable over RS-232. -
Page 31: Description Of The Micro-Line
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 31 6 Description of the micro-line ® Board Connectors 6.1 Location of the Connectors ® For the micro-line connectors, Pin 1 is marked by a black square in Figure 6. connector A connector B connector BB... -
Page 32: Connector Overview
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 32 6.2 Connector Overview ® Table 10 gives an overview about usage of the micro-line connectors, including the 'classic' usage as peripheral interface as used with previous CPU boards. -
Page 33: Table 12: Pinout Summary For The Mcbsp Interfaces
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 33 ® Default shared with micro-line connector signal name Interface signal CLKX0 McASP0 ACLKX0 FSX0 AFSX0 AXR0[1] CLKR0 ACLKR0 FSR0 AFSR0 AXR0[0]... -
Page 34: Table 15: Pinout Summary And Signal Routing For The Mcasp Interfaces
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 34 ® Signal shared with micro-line connector interface signal AXR0[7] McBSP FSR1 AXR0[6] CLKR1 AXR0[5] AXR0[4] Timer TOUT1 AXR0[3] TINP0 AXR0[2] TOUT0... -
Page 35: Pinout Of The Jtag Connector
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 35 6.4 Pinout of the JTAG Connector Signal signal used for FPGA_TMS FPGA FPGA_TDI FPGA_TDO FPGA_TCK +3.3 V not connected not connected unused CPU_EMU0... -
Page 36: Function Of The Micro-Line Connector Pins
This signal is only routed to the FPGA in default hardware configuration, therefore SCL0 is not available by default. In this case, SCL0 can be used for any purpose by an ORSYS board support package or a custom FPGA design. Optionally, SCL0 can additionally be connected to the DSP's C interface #0, see chapter 7.2.5 for details. -
Page 37: Connector D
This is an inverted /RESETOUT signal, that means an active high reset signal. Pins D10 through D16: These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as the FPGA is not loaded. -
Page 38: Connector E
3.10.4) Pin D30: This signal is routed to the FPGA. Usage of the signal requires either an ORSYS board support package or a custom FPGA design. In default hardware configuration, this signal is pulled high by a 4.7KΩ pull-up resistor. Hardware configuration can also be changed to a pull-down resistor, see chapter 7.2.4 for details. - Page 39 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 39 DX1 / AXR0[5]: This pin has a dual function: • If configured for McBSP usage, this pin is the data transmit output of McBSP1. All outgoing data to devices, connected to the McBSP1 is communicated via this output pin.
- Page 40 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 40 CLKS1 / SCL1: This pin has a dual function: • If configured for McBSP usage, this pin is the external input of the internal sample rate generator used for McBSP1.
- Page 41 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 41 DR0 / AXR0[0]: This pin has a dual function: • If configured for McBSP usage, this pin is the data receive input of McBSP0. All incoming data from devices connected to the McBSP is communicated via this input pin.
- Page 42 Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 42 FSR0 / AFSR0: This pin has a dual function: • If configured for McBSP usage, this pin is the receiver frame sync input or output of McBSP0.
- Page 43 : 43 Pins E30 and E31: These signals are routed to the FPGA. Usage of these signals requires either an ORSYS board support package or a custom FPGA design. These signals are pulled-up by the FPGA as long as the FPGA is not loaded and have 22R series resistors.
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Page 44: Environment
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 44 7 Environment 7.1 Minimum Connections ® This chapter shows how to set up the C6713CPU for use without a micro-line Power Supply carrier board. -
Page 45: Figure 9: Connecting The Serial Interface (Rs-232) To A Pc
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 45 standard PC RS-232 connector Sub-D 9pin socket; fits directly into a PC front view CTS (connect to PC's RTS) RxD (connect to PC's TxD) RTS (connect to PC's CTS) TxD (connect to PC's RxD) -
Page 46: Changing The Board Configuration
This chapter shows the different hardware board configurations. The factory defaults are listed below. Some configuration settings may be changed by the user and are described in the subsequent paragraphs. For changing other settings, please contact ORSYS. Function default setting... -
Page 47: Configuring Dsp Clock Speed
The decision which interface is active is controlled by different components and is not available for modification by the user. Default setting is to use the HPI. If McASP1 is to be used, please contact ORSYS. ®... -
Page 48: Configuring Clks1 / Scl1 Termination
HSWAP_EN = 1 disables the pull-up resistors while HSWAP_EN = 0 (default) enables the pull-up resistors. The default setting is to have pull-up resistors enabled and is required by the Flash File System. Please contact ORSYS if this setting has to be changed. 7.3 Signal Levels and Loads 7.3.1... -
Page 49: Supply Voltage
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 49 7.4 Supply Voltage The C6713CPU must be supplied with a voltage of nominal +3.3 V. The integrated switching voltage regulators generate all necessary on-board voltages. -
Page 50: Dimensions Of The Board
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 50 7.9 Dimensions of the Board Figure 12 shows the dimensions of the C6713CPU. When the C6713CPU is stacked with other modules, board spacing is 14mm. -
Page 51: Figure 13: Complete Micro-Line ® Footprint
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 51 78,74 5.71 5.71 2.54 5.71 5.71 15,24 17.78 17.78 ® Figure 13: Complete micro-line footprint... -
Page 52: Spare Micro-Line Connectors
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 52 ® 7.10 Spare micro-line Connectors The C6713CPU uses square connectors with 0.1 inch (2.54 mm) spacing. In contrast to previous ®... -
Page 53: List Of Abbreviations Used In This Document
Date : 28 November 2005 Doc. no. : C6713CPU_HRG ARDWARE EFERENCE UIDE ® Iss./Rev : 1.1 C6713CPU MICRO LINE Page : 53 8 List of abbreviations used in this document board support package: a combination of software and FPGA design that provides further functionality to the C6713CPU Code Composer Studio –TI's development environment Central Processing Unit = processor... -
Page 54: Literature References
[18] , TI, TMP100 temperature sensor data sheet SBOS231 [19] , Macronix, MX29LV160CT/CB 16 Megabit Flash Memory PM1186 [20] , Orsys, C6713CPU DSP Development Kit User’s Guide C6713CPU_DSP_DevKit_ug [21] , Orsys, ® C6713CPU micro-line Busmaster Board Support Package C6713CPU_ML_BM_ug [22]...
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