User Manuals: NXP Semiconductors MSC8158E Access

Manuals and User Guides for NXP Semiconductors MSC8158E Access. We have 1 NXP Semiconductors MSC8158E Access manual available for free PDF download: Reference Manual

NXP Semiconductors MSC8158E Reference Manual

NXP Semiconductors MSC8158E Reference Manual (2358 pages)

Broadband Wireless Access Six Core DSP With Security

Brand: NXP Semiconductors | Category: Wireless Router | Size: 43 MB

Table of Contents

Table of Contents
5
MSC8158E Reference Manual
66
Before Using this Manual-Important Note
68
Audience and Helpful Hints
68
Notational Conventions and Definitions
69
Conventions for Registers
70
Organization
70
Other MSC8158E Documentation
73
Further Reading
73
Document Change History
74
Overview
77
Features
78
Block Diagram
93
Architecture
93
Starcore SC3850 DSP Subsystem
94
Starcore SC3850 DSP Core
95
L1 Instruction Cache
96
L1 Data Cache
96
L2 Unified Cache/M2 Memory
97
Memory Management Unit (MMU)
97
Debug and Profiling Unit (DPU)
97
Extended Programmable Interrupt Controller
98
Timer
98
Maple-B2
99
Security Engine (SEC)
99
Chip-Level Arbitration and Switching System (CLASS)
100
M3 Memory
100
Clocks
101
DDR Controller (DDRC)
101
DMA Controller
102
High Speed System Interface
103
Class1
103
OCN Fabric
104
OCN-To-Mbus (O2M) Bridges
104
DMA Controllers
104
Serial Rapidio Complex
104
Protocol Converter
105
Serdes PHY Interfaces
105
QUICC Engine Subsystem
105
Ethernet Controllers
106
Serial Peripheral Interface (SPI)
106
Global Interrupt Controller (GIC)
107
Uart
107
Timers
107
Hardware Semaphores
107
Virtual Interrupts
107
I 2 C Interface
108
Gpios
108
Boot Options
108
Jtag
108
Developer Environment
108
Tools
109
Application Software
110
SC3850 Core Overview
111
Core Architecture Features
112
Starcore SC3850 Core Architecture
114
Power Signals
120
Clock Signals
121
Reset and Configuration Signals
122
Memory Controller
127
SGMII Interfaces
128
CPRI Signals
129
Ethernet Signals
132
Serial Peripheral Interface (SPI) Signal Summary
134
Gpio/Maskable Interrupt Signal Summary
135
Timer Signals
140
UART Signals
142
I 2 C Signals
143
External DMA Signals
143
Other Interrupt Signals
144
OCE Event and JTAG Test Access Port Signals
145
Chip-Level Arbitration and Switching System (CLASS)
147
CLASS Features
148
Functional Description
149
Expander Module and Transaction Flow
150
Multiplexer and Arbiter Module
150
CLASS Arbiter
150
Weighted Arbitration
151
Late Arbitration
151
Priority Masking
151
Auto Priority Upgrade
151
CLASS Multiplexer
151
Normalizer Module
152
CLASS Control Interface (CCI)
152
CLASS Error Interrupts
152
CLASS Debug Profiling Unit
153
Profiling
153
Watch Point Unit
154
Event Selection
155
Debug and Profiling Events
158
CLASS Reset
158
Soft Reset
158
Hard Reset
158
Limitations
159
Programming Model
160
CLASS Priority Mapping Registers (C0Pmrx)
161
CLASS Priority Auto Upgrade Value Registers (C0Pavrx)
162
CLASS Priority Auto Upgrade Control Registers (C0Pacrx)
163
CLASS Error Address Registers (C0Earx)
164
CLASS Error Extended Address Registers (C0Eearx)
165
CLASS Initiator Profiling Configuration Registers (C0Ipcrx)
166
CLASS Initiator Watch Point Control Registers (C0Iwpcrx)
168
CLASS Arbitration Weight Registers (C0Awrx)
169
CLASS Start Address Decoder X (C0Sadx)
170
CLASS End Address Decoder X (C0Eadx)
171
CLASS Attributes Decoder 1 (C0ATD1)
172
CLASS Attributes Decoder X (C0Atdx)
174
CLASS IRQ Status Register (C0ISR)
175
CLASS IRQ Enable Register (C0IER)
176
CLASS Target Profiling Configuration Register (C0TPCR)
176
CLASS Profiling Control Register (C0PCR)
178
CLASS Watch Point Control Registers (C0WPCR)
179
CLASS Watch Point Access Configuration Register (C0WPACR)
180
CLASS Watch Point Extended Access Configuration Register
181
CLASS Watch Point Address Mask Registers (C0WPAMR)
182
CLASS Profiling Time-Out Registers (C0PTOR)
183
CLASS Target Watch Point Control Registers (C0TWPCR)
184
CLASS Profiling IRQ Status Register (C0PISR)
185
CLASS Profiling IRQ Enable Register (C0PIER)
186
CLASS Profiling Reference Counter Register (C0PRCR)
186
CLASS Profiling General Counter Registers (C0Pgcrx)
187
CLASS Arbitration Control Register (C0ACR)
188
Reset
189
Reset Operations
189
Reset Sources
190
Reset Actions
190
Power-On Reset Flow
191
Detailed Power-On Reset Flow
191
HRESET Flow
194
Reset Configuration
194
Reset Configuration Signals
195
Reset Configuration Words Source
195
Reset Configuration Input Signal Selection and Reset Sequence Duration
196
Reset Configuration Words
196
Loading the Reset Configuration Words
196
Using the Boot Sequencer for Reset Configuration
197
EEPROM Slave Address
197
EEPROM Data Format in Reset Configuration Mode
197
Loading Multiple Devices from a Single I
198
C Eeprom
198
Loading Reduced RCW from External Pins (RCW_SRC[0-2] = 011)
201
Reduced External Reset Configuration Word Low Field Values
201
Reduced External Reset Configuration Word High Field Values
202
Default Reset Configuration Words (RCW_SRC[0-2] = 100 or 101)
202
Hard Coded Reset Configuration Word Low Field Values
202
Hard Coded Reset Configuration Word High Field Values
203
Reset Programming Model
204
Reset Configuration Word Low Register (RCWLR)
204
Reset Configuration Word High Register (RCWHR)
208
Reset Status Register (RSR)
210
Reset Protection Register (RPR)
212
Reset Control Register (RCR)
213
Reset Control Enable Register (RCER)
214
Boot Program
215
Functional Description
216
Private Configuration
217
Shared Configuration
217
Patch Mode
218
Multi Device Support for the I C Bus
218
Example Configuration
220
Boot Modes
223
I 2 C Eeprom
223
Ethernet
228
DHCP Client
229
TFTP Client
230
Boot File Format
230
Simple Ethernet Boot
232
Simple Ethernet Boot Flow
232
Simple Ethernet Boot Ports
233
Boot File Format
234
Serial Rapidio Interconnect
235
Serial Rapidio Interface Without I C Support
235
Serial Rapidio Interface with I2C Support
236
Spi
236
Jump to User Code
237
System after Boot
237
Boot Errors
238
Clock Generation Components and Modes
240
System Clock Control Register (SCCR)
242
Programming Model
243
Detailed Register Descriptions
245
General Configuration Register 1 (GCR1)
246
General Configuration Register 2 (GCR2)
246
General Status Register 1 (GSR1)
248
High Speed Serial Interface Status Register (HSSI_SR)
250
DDR General Control Register (DDR_GCR)
253
High Speed Serial Interface Control Register 1 (HSSI_CR1)
254
High Speed Serial Interface Control Register 2 (HSSI_CR2)
257
QUICC Engine Control Register (QECR)
258
GPIO Pull-Up Enable Register (GPUER)
259
GPIO Input Enable Register (GIER)
260
System Part and Revision ID Register (SPRIDR)
261
General Control Register 4 (GCR4)
262
General Control Register 5 (GCR5)
262
General Status Register 2 (GSR2)
266
Core Subsystem Slave Port Priority Control Register (TSPPCR)
268
General Status Register 3 (GSR3)
269
General Control Register 6 (GCR6)
271
General Control Register 7 (GCR7)
272
General Control Register 8 (GCR8)
275
General Control Register 10 (GCR10)
276
General Interrupt Register 1 (GIR1)
277
General Interrupt Enable Register 1 (Gier1_X)
279
General Interrupt Register 3 (GIR3)
280
General Interrupt Enable Register 3 for Cores 0-3 (Gier3_X)
282
General Interrupt Register 5 (GIR5)
284
General Interrupt Enable Register 5 (Gier5_X)
286
General Control Register 11 (GCR11)
288
General Control Register 13 (GCR13)
289
General Status Register 8 (GSR8)
290
DMA Request0 Control Register (GCR_DREQ0)
291
DMA Request1 Control Register (GCR_DREQ1)
295
DMA Done Control Register (GCR_DDONE)
299
DDR Controller General Configuration Register (DDRC_GCR)
302
Core Subsystem Slave Port General Configuration Register
304
(Core_Slv_Gcr)
304
QUICC Engine Input General Control Register (QE_PIO_IN_GCR)
305
QUICC Engine Output General Status Register (QE_PIO_OUT_GSR)
306
L2Q Arbitration Control for Core Subsystems 0 and 1
307
(Mex_T2_0_1_Arb)
307
L2Q Arbitration Control for Core Subsystems 2 and 3
308
(Mex_T2_2_3_Arb)
308
L2Q Arbitration Control for Core Subsystems 4 and 5
309
(Mex_T2_4_5_Arb)
309
General Interrupt Register 6 (GIR6)
310
General Interrupt Enable Register 6 (Gier6_X)
313
General Interrupt Register 7 (GIR7)
316
General Interrupt Enable Register 7 (Gier7_X)
318
DDR View through L2 Memory Core Subsystems 0-3 (L2MAP_0_3)
321
DDR View through L2 Memory Core Subsystems 4-5 (L2MAP_4_5)
322
Emsg to QUICC Engine External Request Enable (CPCEER)
323
RGMII1 High Resolution Delay Register (UCC1_DELAY_HR)
326
RGMII2 High Resolution Delay Register (UCC3_DELAY_HR)
328
General Interrupt Register 8 (GIR8)
330
CPRI to MAPLE External Request Enable (MAPLE_EXT_REQ_EN_1)
331
Memory Map
333
Shared Memory Address Space
333
Shared SC3850 DSP Core Subsystem M2/L2 Memories
334
SC3850 DSP Core Subsystem Internal Address Space
337
CCSR Address Space
337
Initiators Views of the System Address Space
339
SC3850 (Data) View of the System Address Space
339
Peripherals View of the System Address Space
340
Security Engine View of the System Address Space
340
Detailed System Memory Map
341
SC3850 DSP Subsystem
445
SC3850 DSP Core Subsystem Features
446
SC3850 Core
447
Instruction Channel
448
Instruction Cache
448
Instruction Fetch Unit
449
Data Channel
449
Data Cache
449
Data Fetch Unit
450
Write-Back Buffer
451
Write-Through Buffer
451
Data Control Unit
451
Write Queue
452
Memory Management Unit (MMU)
452
L2 Cache
453
On-Chip Emulator and Debug and Profiling Unit
454
Extended Programmable Interrupt Controller
455
Timer
455
Interfaces
455
Qbus to Mbus Interface Bridge
455
Mbus to DMA Bridge
455
Entering and Exiting Wait and Stop States Safely
456
Wait State
456
Stop State
456
Procedure for Entering DSP Subsystem Stop State Safely
456
Procedure for Exiting the Stop State Safely
457
Programming Restrictions
457
Internal Memory Subsystem
459
Memory Management Unit (MMU)
460
Instruction Channel (Icache and IFU)
461
Data Channel and Write Queue (Dcache)
463
L2 Unified Cache/M2 Memory
466
M3 Memory
470
Internal Boot ROM
470
DDR SDRAM Memory Controller
471
DDR Memory Controller Features
472
DDR Memory Controller Modes of Operation
472
DDR Controller Functional Description
473
DDR SDRAM Interface Operation
477
Supported DDR SDRAM Organizations
478
DDR SDRAM Address Multiplexing
478
JEDEC Standard DDR SDRAM Interface Commands
481
DDR SDRAM Interface Timing
483
Clock Distribution
486
DDR SDRAM Mode-Set Command Timing
487
DDR SDRAM Registered DIMM Mode
488
DDR SDRAM Write Timing Adjustments
489
DDR SDRAM Refresh
490
DDR SDRAM Refresh Timing
491
DDR SDRAM Refresh and Power-Saving Modes
492
Self-Refresh in Sleep Mode
493
DDR Data Beat Ordering
494
Page Mode and Logical Bank Retention
494
Error Checking and Correcting (ECC)
494
Error Management
496
Initialization/Application Information
497
Programming Summary
500
DDR SDRAM Initialization Sequence
502
Self-Refresh Mode Usage
502
Software Based Self-Refresh Scheme
502
Bypassing Re-Initialization During Battery-Backed Operation
503
Memory Controller Programming Model
503
Chip-Select X Bounds Register (Csx_Bnds)
505
Chip-Select X Configuration Register (Csx_Config)
506
Chip-Select X Configuration Register 2 (Csx_Config_2)
508
DDR SDRAM Timing Configuration 3 Register (TIMING_CFG_3)
509
DDR SDRAM Timing Configuration Register 0 (TIMING_CFG_0)
512
DDR SDRAM Timing Configuration Register 1 (TIMING_CFG_1)
515
DDR SDRAM Timing Configuration Register 2 (TIMING_CFG_2)
518
DDR SDRAM Control Configuration Register (DDR_SDRAM_CFG)
524
DDR SDRAM Mode Configuration Register (DDR_SDRAM_MODE)
527
DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)
528
DDR SDRAM Interval Configuration Register (DDR_SDRAM_INTERVAL)
531
DDR SDRAM Data Initialization Register (DDR_DATA_INIT)
532
DDR SDRAM Clock Control Configuration Register (DDR_SDRAM_CLK_CNTL)
533
DDR SDRAM Initialization Address Register (DDR_INIT_ADDR)
534
DDR Initialization Enable Register (DDR_INIT_EN)
535
DDR SDRAM Timing Configuration 4 Register (TIMING_CFG_4)
536
DDR SDRAM Timing Configuration 5 Register (TIMING_CFG_5)
538
DDR ZQ Calibration Control Register (DDR_ZQ_CNTL)
540
DDR Write Leveling Control Register (DDR_WRLVL_CNTL)
542
DDR Write Leveling Control 2 Register (DDR_WRLVL_CNTL_2)
545
DDR Write Leveling Control 3 Register (DDR_WRLVL_CNTL_3)
548
DDR Self Refresh Counter Register (DDR_SR_CNTR)
551
DDR SDRAM Register Control Words 1 Register (DDR_SDRAM_RCW_1)
552
DDR SDRAM Register Control Words 2 Register (DDR_SDRAM_RCW_2)
553
DDR Debug Status Register 1 (DDRDSR_1)
556
DDR Debug Status Register 2 (DDRDSR_2)
557
DDR Control Driver Register 1 (DDRCDR_1)
557
DDR Control Driver Register 2 (DDRCDR_2)
561
DDR SDRAM IP Block Revision 1 Register (DDR_IP_REV1)
562
DDR SDRAM IP Block Revision 2 Register (DDR_IP_REV2)
562
DDR Memory Test Control Register (DDR_MTCR)
563
DDR Data Memory Test Pattern X Register (Ddr_Mtpx)
564
DDR SDRAM Memory Data Path Error Injection Mask High Register (DATA_ERR_INJECT_HI)
565
DDR SDRAM Memory Data Path Error Injection Mask Low Register (DATA_ERR_INJECT_LO)
566
DDR SDRAM Memory Data Path Error Injection Mask ECC Register
567
Err_Inject
567
DDR SDRAM Memory Data Path Read Capture Data High Register (CAPTURE_DATA_HI)
568
DDR SDRAM Memory Data Path Read Capture Data Low Register (CAPTURE_DATA_LO)
568
DDR SDRAM Memory Data Path Read Capture ECC Register
569
Capture_Ecc
569
DDR SDRAM Memory Error Detect Register (ERR_DETECT)
569
DDR SDRAM Memory Error Disable Register (ERR_DISABLE)
571
DDR SDRAM Memory Error Interrupt Enable Register (ERR_INT_EN)
572
DDR SDRAM Memory Error Attributes Capture Register (CAPTURE_ATTRIBUTES)
573
DDR SDRAM Memory Error Address Capture Register (CAPTURE_ADDRESS)
574
DDR SDRAM Single-Bit ECC Memory Error Management Register
575
Err_Sbe
575
Interrupt Handling
577
Global Interrupt Controller (GIC)
579
General Configuration Block
580
Interrupt Groups Toward the SC3850 Cores
581
Interrupt Groups Toward QUICC Engine Processors
582
External Interrupts
582
Interrupt Groups Directed Toward MAPLE-B2
583
Interrupt Handling
584
Interrupt Mapping
585
Core Interrupt Mesh
601
Programming Model
602
Global Interrupt Controller
602
Virtual Interrupt Generation Register (VIGR)
602
Virtual Interrupt Status Register (VISR)
603
General Interrupt Configuration
605
Programming Restrictions
606
Direct Memory Access (DMA) Controller
607
Operating Modes
608
Buffer Types
609
One-Dimensional Simple Buffer
610
One-Dimensional Cyclic Buffer
611
One-Dimensional Chained Buffer
612
One-Dimensional Incremental Buffer
613
One-Dimensional Complex Buffers with Dual Cyclic Buffers
614
Two-Dimensional Simple Buffer
615
Three-Dimensional Simple Buffer
617
Four-Dimensional Simple Buffer
618
Multi-Dimensional Chained Buffer
621
Two-Dimensional Cyclic Buffer
623
Three-Dimensional Cyclic Buffer
624
Arbitration Types
625
Round-Robin Arbitration
625
EDF Arbitration
626
Issuing Interrupts
627
Counter Control
627
Clock Source to the Counters
628
Interrupts
628
Maskable Interrupts
628
Nonmaskable Interrupts
628
DMA Peripheral Interface
629
Modes of Operation
629
Configuration and Control Registers
630
Functional Description
631
Request Signal
631
Done Signal
631
Signal Operation
631
Using the DMA Peripheral Interface Block
632
DMA Programming Model
633
DMA Buffer Descriptor Base Registers X (Dmabdbrx)
634
DMA Controller Channel Configuration Registers X (Dmachcrx)
635
DMA Controller Global Configuration Register (DMAGCR)
637
DMA Channel Enable Register (DMACHER)
637
DMA Channel Disable Register (DMACHDR)
638
DMA Channel Freeze Register (DMACHFR)
639
DMA Channel Defrost Register (DMACHDFR)
639
DMA Time-To-Dead Line Registers X (Dmaedftdlx)
640
DMA EDF Control Register (DMAEDFCTRL)
641
DMA EDF Mask Register (DMAEDFMR)
641
DMA EDF Mask Update Register (DMAEDFMUR)
642
DMA EDF Status Register (DMAEDFSTR)
644
DMA Mask Register (DMAMR)
644
DMA Mask Update Register (DMAMUR)
645
DMA Status Register (DMASTR)
646
DMA Error Register (DMAERR)
647
DMA Debug Event Status Register (DMADESR)
649
DMA Round-Robin Priority Group Update Register (DMARRPGUR)
649
DMA Channel Active Status Register (DMACHASTR)
650
DMA Channel Freeze Status Register (DMACHFSTR)
650
DMA Channel Buffer Descriptors
651
Buffer Attributes (BD_ATTR)
654
Multi-Dimensional Buffer Attributes (BD_MD_ATTR)
657
High Speed Serial Interface (HSSI) Subsystem
663
HSSI Subsystem Block Diagram
664
Class1
665
Functional Description
666
Expander Module and Transaction Flow
666
Multiplexer and Arbiter Module
666
CLASS Arbiter
667
CLASS Multiplexer
668
Normalizer Module
668
CLASS1 Control Interface (C1CI)
668
CLASS Error Interrupts
668
CLASS Debug Profiling Unit
669
Profiling
669
Watch Point Unit
670
Event Selection
671
Debug and Profiling Events
674
CLASS Reset
674
Limitations
674
OCN Fabric
674
OCN-To-Mbus (O2M) Bridges
675
DMA Controllers
675
Overview
676
Features
676
Modes of Operation
676
DMA Channel Operation
678
Basic DMA Mode Transfer
678
Basic Direct Mode
679
Basic Direct Single-Write Start Mode
679
Basic Chaining Mode
680
Basic Chaining Single-Write Start Mode
681
Extended DMA Mode Transfer
681
Extended Direct Mode
681
Extended Direct Single-Write Start Mode
682
Extended Chaining Mode
682
Extended Chaining Single-Write Start Mode
682
Channel Continue Mode for Cascading Transfer Chains
683
Basic Mode
684
Extended Mode
684
Channel Abort
684
Bandwidth Control
684
Channel State
685
Illustration of Stride Size and Stride Distance
685
DMA Transfer Interfaces
686
DMA Errors
686
DMA Descriptors
686
Local Access ATMU Registers
689
Limitations and Restrictions
689
Serial Rapidio Complex
690
Protocol Converter
690
Serdes PHY Interfaces
690
Serdes Banks and PLL
691
Serdes PLL Reference Clocks
691
Serdes PLL Multiplexing
692
Serdes Clocks
693
HSSI Programming Model
694
CLASS1 Priority Mapping Registers (C1Pmrx)
697
CLASS1 Priority Auto Upgrade Value Registers (C1Pavrx)
698
CLASS1 Priority Auto Upgrade Control Registers (C1Pacrx)
699
CLASS1 Error Address Registers (C1Earx)
700
CLASS1 Error Extended Address Registers (C1Eearx)
701
CLASS1 Initiator Profiling Configuration Registers (C1Ipcrx)
702
CLASS1 Initiator Watch Point Control Registers (C1Iwpcrx)
703
CLASS1 Arbitration Weight Registers (C1Awrx)
704
CLASS1 Start Address Decoder 1 (C1SAD1)
705
CLASS1 Start Address Decoder 2(C1SAD2)
706
CLASS1 End Address Decoder 1 (C1EAD1)
707
CLASS1 End Address Decoder 1 (C1EAD2)
708
CLASS1 Attributes Decoder 1 (C1ATD1)
709
CLASS1 Attributes Decoder 1 (C1ATD2)
711
CLASS1 IRQ Status Register (C1ISR)
712
CLASS1 IRQ Enable Register (C1IER)
714
CLASS1 Target Profiling Configuration Register (C1TPCR)
715
CLASS1 Profiling Control Register (C1PCR)
716
CLASS1 Watch Point Control Registers (C1WPCR)
717
CLASS1 Watch Point Access Configuration Register (C1WPACR)
719
CLASS1 Watch Point Extended Access Configuration Register
720
C1Wpeacr
720
CLASS1 Watch Point Address Mask Registers (C1WPAMR)
721
CLASS1 Profiling Time-Out Registers (C1PTOR)
722
CLASS1 Target Watch Point Control Registers (C1TWPCR)
723
CLASS1 Profiling IRQ Status Register (C1PISR)
724
CLASS1 Profiling IRQ Enable Register (C1PIER)
725
CLASS1 Profiling Reference Counter Register (C1PRCR)
726
CLASS1 Profiling General Counter Registers (C1Pgcrx)
727
CLASS1 Arbitration Control Register (C1ACR)
728
Mode Registers 0-3 (Dnmr[0-3])
729
Status Registers (Dnsrn)
732
Current Link Descriptor Extended Address Registers (Dneclndarn)
734
Current Link Descriptor Address Registers (Dnclndarn)
735
Source Attributes Registers (Dnsatrn)
736
Source Address Registers (Dnsarn)
737
Destination Attributes Registers (Dndatrn)
738
Destination Address Registers (Dndarn)
739
Byte Count Registers (Dnbcrn)
740
Extended Next Link Descriptor Address Registers (Dnenlndarn)
741
Next Link Descriptor Address Registers (Dnnlndarn)
742
Extended Current List Descriptor Address Registers (Dneclsdarn)
743
Current List Descriptor Address Registers (Dnclsdarn)
744
Extended Next List Descriptor Address Registers (Dnenlsdarn)
745
Next List Descriptor Address Registers (Dnnlsdarn)
746
Source Stride Registers (Dnssrn)
747
Destination Stride Registers (Dndsrn)
748
DMA General Status Register (Dndgsr))
749
Local Access Window Base Address Registers 0-9 (Dnlawbar[0-9])
751
Local Access Window Attributes Registers 0-9 (Dnlawar[0-9])
752
Cprin PCVTR Control Register 0(Pcvtrcprincr0)
754
Cprin PCVTR Control Register 1(Pcvtrcprincr1)
755
SRDS Bank 1 Reset Control Register (SRDSB1RSTCTL)
756
SRDS Bank 2 Reset Control Register (SRDSB2RSTCTL)
757
SRDS Bank 1-2 PLL Control Register 0 (SRDSB[1-2]PLLCR0)
758
SRDS Bank 1-2 PLL Control Register 1 (SRDSB[1-2]PLLCR1)
759
Lane C-J General Control Register 0 (L[C-J]GCR0)
760
Lane C-J General Control Register 1 (L[C-J]GCR1)
761
Lane C-J Receive Equalization Control Register 0 (L[C-J]RECR0)
762
Lane C-J Transmit Equalization Control Register 0 (L[C-J]TECR0)
764
Lane C-J Test Control/Status Register 3 (L[C-J]TCSR3)
766
Serial Rapidio Controller and Enhanced Message Complex
767
Serial Rapidio and Emsg Complex Overview
770
Serial Rapidio Ports
770
Emsg Unit
771
Internal Processing Support
773
Operating Modes
774
X1/X2/X4 LP-Serial Signals
774
Rapidio Interface Activation
775
Initialization for Booting the MSC8158E DSP
775
Initialization for Non-Boot Operation
775
Link Training
775
Initialize Link
776
Reset Link
776
Software Retraining
777
Special Case of X2/X1 Modes
777
Rapidio Interface Basics
778
Rapidio Transactions
778
Message Passing
780
Rapidio Data Streaming (Type9) Transactions
780
Rapidio GSM Transactions
781
Rapidio Packet Format
781
Rapidio Control Symbol Summary
783
Accessing Configuration Registers Via Rapidio Packets
784
Inbound Maintenance Accesses
784
Guidelines
785
Outbound Maintenance Accesses
785
Interaction with the Message Unit
785
Inbound (Rx)
786
Outbound (Tx)
786
Buffer Allocation
786
Tx Message Unit Request Packets
787
Tx Message Unit Response/Flow Control Packets
788
Arbitration
789
Arbitration Point 0
789
Arbitration Point 1
790
Arbitration Point 2
790
Rapidio ATMU Implementation
790
Rapidio Outbound ATMU
791
Outbound Windows
793
Window Size and Segmented Windows
793
Valid Hits to Multiple ATMU Windows
818
Window Boundary Crossing Errors
819
Rapidio Inbound ATMU
820
Hits to Multiple ATMU Windows
822
Window Boundary Crossing Errors
822
Generating Link-Request/Reset-Device
823
Outbound Drain Mode
824
Input Port Disable Mode
825
Software Assisted Error Recovery Register Support
825
Errors and Error Handling
826
Rapidio Error Description
826
Physical Layer Rapidio Errors
827
Logical Layer Rapidio Errors
830
Rapidio Enhanced Message Unit (Emsg) Communication
856
Overview
856
Modes of Operation
858
Outbound Modes of Operation
858
Inbound Modes of Operation
858
Command Descriptor Format
859
Inbound Command Descriptor Format
859
Outbound Command Descriptor Format
861
Outbound Completion Queues
862
Scatter/Gather Tables
863
Type5 Nwrite Unit Functional Description
865
Type5 Outbound Nwrite Descriptor Format
865
Type5 Outbound Nwrite Operation
868
Work Scheduling
868
Adding Nwrites to a Message Queue
868
Nwrite Initialization
869
Error Handling
869
Descriptor Error
870
Transaction Errors
870
Type6 Streaming Write Functional Description
871
Type6 Outbound Swrite Descriptor Format
871
Type6 Outbound Swrite Operation
873
Work Scheduling
874
Descriptor Error
875
Type8 Port-Write Functional Description
876
Type8 Inbound Port-Write Descriptor Format
878
Type8 Outbound Port-Write Operation
879
Port-Write Initialization
880
Descriptor Error
881
Type8 Inbound Port-Write Operation
882
Buffer Size Errors
883
Type9 Reassembly Descriptor Format
886
Type9 Outbound Segmentation Operation
889
Segmentation Initialization
890
Descriptor Error
891
Type9 Reassembly Operation
892
Single/Start Segment Error
894
Segment Request Timeout Errors
895
Flow Control Management
896
Sending Flow Control Messages
897
Type10 Doorbell Functional Description
898
Type10 Inbound Doorbell Descriptor Format
901
Type10 Outbound Doorbell Operation
903
Doorbell Initialization
904
Descriptor Error
905
Doorbell Error Response Errors
906
Type10 Inbound Doorbell Operation
907
Error Handling
908
Transaction Errors
909
Type11 Inbound Message Descriptor Format
913
Type11 Outbound Message Operation
915
Adding Messages to a Message Queue
916
Descriptor Error
918
Multicast Errors
919
Type11 Inbound Message Operation
920
Error Handling
921
Segment Request Time-Out Errors
922
Buffer Size Errors
923
Classification
924
Segmentation and Reassembly
925
Examples
928
Address Alignment Requirements
932
Outbound Segmentation Interleaving
933
Transaction Priorities
934
Interrupts
935
Dynamically Changing Rules
937
Initializing Outbound Message Queues
938
Message Unit Reassembly Context Assignment Registers
946
Rapidio Registers
947
Device Information Capability Register (DICAR)
948
Assembly Information Capability Register (AICAR)
949
Processing Element Features Capability Register (PEFCAR)
950
Source Operations Capability Register (SOCAR)
951
Destination Operations Capability Register (DOCAR)
952
Data Streaming Information Capability Register (DSICAR)
954
Base Device ID Command and Status Register (BDIDCSR)
957
Component Tag Command and Status Register (CTCSR)
958
Port Maintenance Block Header 0 (PMBH0)
959
Port General Control Command and Status Register (PGCCSR)
961
Port 1–2 Local Ackid Command and Status Register (Pnlascr)
964
Port 1–2 Error and Status Command and Status Register (Pnescsr)
965
Port 1–2 Control Command and Status Register (Pnccsr)
966
Error Reporting Block Header (ERBH)
969
Status Register
971
Port 1–2 Error Detect Command and Status Register (Pnedcsr)
976
Port 1–2 Error Rate Command and Status Register (Pnercsr)
982
Logical Layer Configuration Register (LLCR)
984
Logical Retry Error Threshold Configuration Register (LRETCR)
985
Physical Retry Error Threshold Configuration Register (PRETCR)
986
Port 1–2 Physical Configuration Register (Pnpcr)
991
Port 1–2 Serial Link Command and Status Register (Pnslcsr)
992
Port N Arbitration 0 Tx Configuration Register (Pna0Txcr)
993
Port N Arbitration 1 Tx Configuration Register (Pna1Txcr)
995
Port N Arbitration 2 Tx Configuration Register (Pna2Txcr)
996
Configuration Register (Pnmrspfctxbacr)
1002
IP Block Revision Register 1 (IPBRR1)
1003
IP Block Revision Register 2 (IPBRR2)
1004
Registers X (Pnrowtearx)
1005
Emsg, Bmlite, and Qmlite Registers
1013
Inbound Block M Type8 Classification N Status Register (Ibmt8Cnsr)
1014
Register 1 (Ibmt8Cnrvr1)
1015
Register 1 (Ibmt8Cnrmr1)
1017
Inbound Block M Type9 Classification N Status Register (Ibmt9Cnsr)
1022
Inbound Block M Type9 Classification N Message Queue Register
1023
Register 1 (Ibmt9Cnrvr1)
1024
Inbound Block M Type10 Classification N Message Queue Register
1033
Register 1 (Ibmt10Cnrmr1)
1035
Register 1 (Ibmt11Cnrvr1)
1042
Inbound Block M Message Queue N Mode Registers (Ibmmqnmr)
1047
Inbound Block M Message Queue N Status Registers (Ibmmqnsr)
1048
Outbound Block M Message Queue N Mode Registers (Obmmqnmr)
1056
Outbound Block M Message Queue N Status Registers (Obmmqnsr)
1058
Outbound Block M Completion Queue Mode Registers (Obmcqmr)
1063
Outbound Block M Completion Queue Status Registers (Obmcqsr)
1064
Software Portal Interrupt Status Register (Swpn_Isr)
1067
Software Portal Interrupt Enable Register (Swpn_Ier)
1068
Software Portal Interrupt Status Disable Register (Swpn_Isdr)
1069
Software Portal Interrupt Inhibit Register (Swpn_Iir)
1070
Registers
1071
Software Portal Acquire Consumer Index (Swpn_Acq_Ci_Ringk)
1075
Software Portal Release Producer Index (Swpn_Rel_Pi_Ringk)
1076
Software Portal Acquire Producer Index (Swpn_Acq_Pi_Ringk)
1077
Software Portal Release Consumer Index (Swpn_Rel_Ci_Ringk)
1079
Message Queue Mode Register (MQMR)
1080
Message Queue Interrupt Enable Register (MQIER)
1082
Message Queue Error Capture Address Register (MQECAR)
1083
S/W Portal Depletion Entry Threshold Register (Poolk_Swdet)
1084
S/W Portal Depletion Count Register (Poolk_Sdcnt)
1085
H/W Portal Depletion Entry Threshold Register (Poolk_Hwdet)
1086
H/W Portal Depletion Exit Threshold Register (Poolk_Hwdxt)
1087
Free List Head Pointer Register (Poolk_Hdptr)
1088
Buffer Pointer Range Release Registers (BPRR_{CFG,START,END})
1091
Free Buffer Proxy Record Free Pool Count (FBPR_FPC)
1093
Free Buffer Proxy Record List Head Pointer Register (FBPR_HDPTR)
1094
Error Interrupt Status Register (ERR_ISR)
1095
Error Interrupt Enable Register (ERR_IER)
1096
Interrupt Status Disable Register (ERR_ISDR)
1097
Error Interrupt Inhibit Register (ERR_IIR)
1098
Single Bit ECC Error Threshold Register (SBET)
1099
External Memory Access Interrupt Capture Register (EMAI_ECR)
1100
External Memory Access Interrupt Address Register (EMAI_EADR)
1101
External Memory Corruption Interrupt Capture Register (EMCI_ECR)
1102
IP Block Revision 1 Register (IP_REV_1)
1103
IP Block Revision 2 Register (IP_REV_2)
1104
Message Unit Mode Register (MUMR)
1105
Message Unit Interrupt Enable Registers (MUIER)
1106
Message Unit Error Detect Registers (MUEDR)
1107
Message Unit Interrupt Coalescing Registers (MUICR)
1108
Message Unit T8 Drop Counter Registers (MUT8DCR)
1109
Message Unit Error Capture MQ Register (MUECMQR)
1110
Message Unit Error Capture CD Register 1 (MUECCDR1)
1111
Message Unit Error Capture CD Register 3 (MUECCDR3)
1112
Message Unit Arbitration Weight Register (MUAWR)
1113
Message Unit Outbound Interleaving Mask Register (MUOIMR)
1114
IP Block Revision Register 0 (IPBRR0) for Emsg
1118
Programming Restrictions
1119
Features
1122
Modes of Operation
1124
CPRI Framer Transmitter
1126
CPRI Framer Receiver
1127
Auto Negotiation (Setup)
1129
Autonegotiation (Setup) Flow
1130
Protocol Setup (State C)
1131
C&M Channel Rate Setup (State D)
1132
DMA Configuration
1133
Advanced Axc Mapping Modes
1137
CPRI IQ MAP Interface Synchronization
1142
Control Words
1143
Control Words Reception
1145
Slow C&M Channel (HDLC)
1147
CPRI DMA Controller
1148
Receive DMA and Transmit DMA Memories
1149
Receive IQ Data Flow
1150
Transmit IQ Data Flow
1153
Receive VSS (Vendor Specific Data) Data Flow
1154
Transmit VSS (Vendor Specific Data) Data Flow
1155
Receive Ethernet Data Flow
1156
Receive Ethernet Interrupts
1158
Ethernet Transmit Interrupts
1159
Receive HDLC Interrupts
1160
HDLC Transmit Interrupts
1161
Chip Rate Mode
1162
Axc Data Buffers
1163
Uplink Delay in Chip Rate Mode
1166
Down Link Latency
1167
Star Topology
1168
CPRI Double Sampling Rate
1170
Timers
1171
Timer Sync State Machine
1173
Interrupts
1174
L1 Inband Protocol Errors
1176
Cp_Los
1177
CPRI Transmission Delay
1179
CPRI Reception Delay
1180
Delay Accuracy
1182
CPRI Framer Registers
1186
CPRI Configuration (Cprin_Config)
1187
CPRI Receive Line Coding Violation Counter (Cprin_Lcv)
1188
CPRI Recovered BFN Counter (Cprin_Bfn)
1189
CPRI Hardware Reset from Control Word (Cprin_Hw_Reset)
1190
CPRI Control and Management Configuration (Cprin_Cm_Config)
1191
CPRI Control and Management Status (Cprin_Cm_Status)
1192
CPRI Receive Delay (Cprin_Rx_Delay)
1193
CPRI Transmit Protocol Version (Cprin_Tx_Prot_Ver)
1195
CPRI Transmit Scrambler Seed (Cprin_Tx_Scr_Seed)
1196
CPRI Receive Scrambler Seed (Cprin_Rx_Scr_Seed)
1197
CPRI Mapping Configuration (Cprin_Map_Config)
1198
CPRI Mapping Counter Configuration (Cprin_Map_Cnt_Config)
1199
Ethernet Receive Status (Cprin_Eth_Rx_Status)
1204
Ethernet Miscellaneous Configuration (Cprin_Eth_Config_2)
1206
Ethernet RX Packet Discard (Cprin_Eth_Rx_Control)
1207
Ethernet 16 MSB of MAC Address (Cprin_Eth_Addr_Msb)
1208
Ethernet 32 LSB of MAC Address (Cprin_Eth_Addr_Lsb)
1209
Ethernet Configuration 3 (Cprin_Eth_Config_3)
1210
Ethernet Receive Frame Counter (Cprin_Eth_Cnt_Rx_Frame)
1211
HDLC Miscellaneous Configuration (Cprin_Hdlc_Config_2)
1213
HDLC RX Packet Discard (Cprin_Hdlc_Rx_Control)
1214
HDLC Configuration 3 (Cprin_Hdlc_Config_3)
1215
HDLC Receive Frame Counter (Cprin_Hdlc_Cnt_Rx_Frame)
1216
CPRI Complex Registers
1217
Transmit IQ Mbus Transaction Size (Cprintiqmts)
1219
Receive VSS Mbus Transaction Size (Cprinrvssmts)
1220
Receive IQ Second Destination Base Address (Cprinriqsdba)
1221
Receive IQ Buffer Size (Cprinriqbs)
1222
Transmit IQ Buffer Size (Cprintiqbs)
1223
Transmit VSS Buffer Size (Cprintvssbs)
1224
Receive HDLC Buffer Size (Cprinrhdlcbs)
1225
Transmit VSS Base Address (Cprintvssba)
1226
Transmit Ethernet BD Ring Base Address (Cprintebdrba)
1227
Transmit HDLC BD Ring Base Address (Cprinthbdrba)
1228
Transmit Ethernet BD Ring Size (Cprintebdrs)
1229
Transmit HDLC BD Ring Size (Cprinthbdrs)
1230
Transmit General CPRI Mode (Cprintgcm)
1231
Transmit Synchronization Configuration Register (Cprintscr)
1232
Transmit CPRI Framer Buffer Size (Cprintcfbs)
1233
Transmit Control Table Insert Enable 1(Cprintctie1)
1234
Transmit Control Table Insert Enable 2(Cprintctie2)
1235
Timer Configuration (Cprintmrc)
1236
Receive Frame Pulse Width (Cprinrfpw)
1238
Transmit Frame Pulse Width (Cprintfpw)
1239
Control Registers
1240
Transmit Control Register (Cprintcr)
1241
Receive Axc Control Register (Cprinraccr)
1242
Transmit Axc Control Register (Cprintaccr)
1244
Receive Control Attribute Register (Cprinrca)
1245
Receive Control Data Register 0 (Cprinrcd0)
1246
Receive Control Data Register 2 (Cprinrcd2)
1247
Transmit Control Attribute Register (Cprintca)
1248
Transmit Control Data Register 0 (Cprintcd0)
1249
Transmit Control Data Register 1(Cprintcd1)
1250
Receive IQ First Threshold (Cprinriqft)
1251
Receive IQ Second Threshold (Cprinriqst)
1252
Receive IQ Threshold (Cprinriqt)
1253
Transmit IQ First Threshold (Cprintiqft)
1254
Transmit IQ Second Threshold (Cprintiqst)
1255
Transmit IQ Threshold (Cprintiqt)
1256
Transmit VSS Threshold (Cprintvsst)
1257
Receive Ethernet Coalescing Threshold (Cprinrethct)
1258
Transmit Ethernet Coalescing Threshold (Cprintethct)
1259
Receive IQ Threshold Second Destination (Cprinriqtsd)
1262
Timer Enable Register (Cprintmre)
1264
Receive Ethernet Write Pointer Ring (Cprinrewpr)
1265
Transmit Ethernet Write Pointer Ring (Cprintewpr)
1266
Receive HDLC Write Pointer Ring (Cprinrhwpr)
1267
Transmit HDLC Write Pointer Ring (Cprinthwpr)
1268
Receive Antenna Carrier Parameter Register <Y> (Cprinracpr<Y>)
1269
Transmit Antenna Carrier Parameter Register <Y> (Cprintacpr<Y>)
1270
CPRI Auxiliary Interface Mask Registers <Y> (Cprinmaskr<Y>)
1271
CPRI Auxiliary Control Register (Cprinauxcr)
1272
Status Registers
1273
Transmit IQ Buffer Displacement Register (Cprintiqbdr)
1274
Receive Chips Counter Register (Cprinrccr)
1275
Receive VSS Buffer Displacement Register (Cprinrvssbdr)
1276
Transmit VSS Buffer Displacement Register (Cprintvssbdr)
1277
Receive Ethernet Buffer Descriptor (Cprinrethbd)
1278
Transmit Ethernet Buffer Descriptor (Cprintethbd)
1279
Receive Ethernet Read Pointer Ring (Cprinrerpr)
1280
Transmit Ethernet Read Pointer Ring (Cprinterpr)
1281
Receive HDLC Buffer Descriptor (Cprinrhdlcbd)
1282
Transmit HDLC Buffer Descriptor (Cprinthdlcbd)
1283
Receive HDLC Read Pointer Ring (Cprinrhrpr)
1284
Transmit HDLC Read Pointer Ring (Cprinthrpr)
1285
Receive Event Register (Cprinrer)
1286
Transmit Event Register (Cprinter)
1287
Error Event Register (Cprineer)
1289
Receive Ethernet Coalescing Status (Cprinrethcs)
1291
Transmit Ethernet Coalescing Status (Cprintethcs)
1292
Receive Status Register (Cprinrsr)
1293
Transmit Status Register (Cprintsr)
1294
Transmit Configuration Memory (Cprintcm_<I>)
1296
CPRI Control Clocks Register (CPRICCR)
1298
CPRI Interrupt Control Register y (Cpriicr<Y>)
1299
CPRI Receive CPU Control Interrupt Enable Register (CPRIRCCIER)
1301
CPRI Transmit CPU Control Interrupt Enable Register (CPRITCCIER)
1303
General Receive Synchronization Register (CPRIGRSR)
1305
General Transmit Synchronization Register (CPRIGTSR)
1306
CPRI Error Status Register (CPRIESR)
1307
Overview
1310
RISC Processors
1311
Peripheral Interface
1312
Buffer Descriptors (Bds)
1313
Multithreading
1314
Serial Numbers (Snums)
1315
Iram
1316
SDMA and Bus Error
1317
Selective Peripheral Recovery Procedure
1318
SDMA Internal Resource
1319
Baud-Rate Generators (Brgs)
1321
Interrupt Controller
1322
UCC Functionality
1323
Multi-Threading Configuration
1325
Operating Modes
1327
Reduced Gigabit Media-Independent Interface (RGMII) Signals
1328
RGMII Signal Configuration
1329
SGMII Signal Configuration
1330
Ethernet Controller Initialization
1331
Ethernet Programming Restrictions
1332
Pause Frame Time
1333
Magic Packet Handling
1334
Malformed Magic Packet Mode Triggers Exit
1335
Serial Peripheral Interface (SPI)
1337
SPI Operating Modes
1338
SPI as a Slave Device
1340
External Signal Configuration
1342
Programming Model
1343
Transmitter
1354
Character Transmission
1355
Break Characters
1357
Idle Characters
1358
Character Reception
1359
Data Sampling
1360
Framing Error
1365
Parity Error
1366
Slow Data Tolerance
1367
Fast Data Tolerance
1368
Idle Input Line Wake-Up (WAKE = 0)
1369
Modes of Operation
1370
Loop Operation
1371
Interrupt Operation
1372
SCI Baud-Rate Register (SCIBR)
1373
SCI Control Register (SCICR)
1374
SCI Status Register (SCISR)
1377
SCI Data Register (SCIDR)
1379
SCI Data Direction Register (SCIDDR)
1380
Device-Level Timers
1381
Features
1383
Setting up Counters for Cascaded Operation
1384
Operation of the Cascaded Timer
1385
One-Shot Mode
1387
Pulse Output Mode
1388
Variable Frequency PWM Mode
1389
Timer Compare Functionality
1391
Compare Preload Registers
1392
Capture Register Use
1393
Resets and Interrupts
1394
Timer Overflow Interrupts
1395
Special CPRI Support
1396
SC3850 DSP Core Subsystem Timers
1397
Modes of Operation
1398
Timers Programming Model
1400
Timer Channel Control Registers (Tmrnctlx)
1402
Timer Channel Status and Control Registers (Tmrnsctlx)
1404
Timer Channel Compare 1 Registers (Tmrncmp1X)
1406
Timer Channel Capture Registers (Tmrncapx)
1408
Timer_32B Channel X Compare 1 Registers (Tmr_32B_N_Cmp1_X)
1409
Timer_32B Channel Capture Registers (Tmr_32B_Ncapx)
1410
Timer_32B Channel Hold Registers (Tmr_32B_N_Holdx)
1411
Timer_32B Channel Control Registers (Tmr_32B_N_Ctlx)
1412
Timer_32B Channel Status and Control Registers (Tmr_32B_N_Scrx)
1415
Timer_32B Global System Timer Register (Tmr_32B_N_Glb)
1419
Timer_32B Timer Set and Forget Register (Tmr_32B_N_Saf)
1422
Timer_32B Timer Clear Lock Register (Tmr_32B_N_Clrl)
1423
SC3850 DSP Core Subsystem Timers
1424
System Watchdog Control Register 0–7 (SWCRR[0–7])
1425
System Watchdog Count Register 0–7 (SWCNR[0–7])
1426
Features
1427
GPIO Block Diagram
1428
GPIO Connection Functions
1429
GPIO Programming Model
1431
Pin Open-Drain Register (PODR)
1432
Pin Data Register (PDAT)
1433
Pin Data Direction Register (PDIR)
1434
Pin Assignment Register (PAR)
1435
Pin Special Options Register (PSOR)
1436
Features
1440
Clock Control
1441
Transaction Monitoring
1442
In/Out Data Shift Register
1443
Functional Description
1444
Target Address Transmission
1445
STOP Condition
1446
Clock Synchronization
1447
Initialization Sequence
1448
Generation of STOP
1449
Target Mode Interrupt Service Routine
1450
Programming Model
1452
Digital Filter Sampling Rate Register (I2CDFSRR)
1457
TAP, Boundary Scan, and OCE
1459
Overview
1460
TAP Controller
1462
Instruction Decoding
1463
Multi-Core JTAG and OCE Module Concept
1467
DEBUG_REQUEST and ENABLE_ONCE Commands
1468
RD_STATUS Command
1469
Signalling a Debug Request
1470
EE_CTRL Modifications for the MSC8158E
1471
ESEL_DM and EDCA_CTRL Register Programming
1472
Exiting Debug Mode
1473
General JTAG Mode Restrictions
1474
Boundary Scan Register (BSR)
1475
Shift Registers
1477
Identification Register
1478
Debug and Profiling
1479
Entering Debug Mode
1480
SC3850 Debug and Profiling
1481
Profiling Unit
1482
QUICC Engine Debug and Profiling
1484
Profiling Unit
1485
Profiling Unit
1486
Functional Description
1487
Performance Monitor Interrupts
1488
Chaining
1489
Performance Monitor Examples
1503
Performance Monitor Programming Model
1505
Performance Monitor Global Control Register (PMGC)
1506
Performance Monitor Local Control A0 Register (PMLCA0)
1507
Performance Monitor Local Control A[1–8] (PMLCA[1–8])
1508
Performance Monitor Counter 0 (PMC0)
1509
Performance Monitor Counter 1–8 (PMC[1–8])
1510
Information Organization
1512
MAPLE-B2 Features
1514
Modes of Operation
1521
Initialization
1522
Initialization Parameters
1523
PE Arbitration between Different Clients
1524
Buffer Descriptor (BD) Ring Handling
1525
BD Arbitration
1526
Bds Data Coherency
1529
Mbus Priority Scheme Configuration
1530
Mbus Dynamic Priority Accesses with DMA Queue Upgrade
1531
MAPLE-B2 Second Generation Programmable System Interface (PSIF2)
1532
Memory Error Correction/Detection Support
1533
MAPLE-B2 Interrupts
1535
General ECC Error Event Interrupt
1536
Handling a General ECC Error Event
1537
Turbo Standard Parameter Assumptions
1538
Input Samples Polarity
1541
Wimax HARQ Input Data Structure
1542
E-DCH HARQ with Mixed Vector Input Data Structure
1543
E-DCH HARQ with Separate Vectors Input Data Structure
1544
Sub-Block Interleaved Input Data Structure
1546
Separate Vectors Input Data Structure
1547
Viterbi Periodically Punctured Stream Input Data Structure
1549
Etvpe Input Data Structures Summary
1551
Rate Matched Code Block Size Calculation
1553
Buffer Size Calculations
1554
Code Block E_Ini Calculation
1555
HARQ Combining
1556
Setting the HARQ Combining Parameters
1558
Calculating the IHBSA Parameter
1559
Sub-Block De-Interleaving
1560
Turbo Decoding
1561
Number of Turbo Processing Elements (Dres)
1563
Turbo Stopping Criteria Configurations
1564
CRC Check Based Stopping Criteria
1565
Stopping Criteria Configuration Limitations
1566
Viterbi Decoding
1567
Viterbi Decoding Algorithm
1568
Feed Forward
1569
Maximum Calculations
1572
Tail Biting Viterbi Processing (WAVA*)
1573
Viterbi Large Blocks Partitioning Support
1574
De-Randomization
1578
Etvpe Output Data Structure
1579
Extrinsic Output Data
1581
Soft Output Data
1582
Hard Output Data
1583
Hard Output Offset
1584
Byte/Bit Ordering Limitations
1586
Eftpe Fft/Ifft/Dft/Idft Operation
1587
Identical Output Scale Alignment for BD Repeat
1589
Eftpe Data Structures
1590
Guard Band Insertion for Ifft
1592
Zero Padding Support
1594
Input Buffers Offset (in Kbs) for FFT BD Repeat
1595
Repeat
1596
Output Data Structure
1597
Cyclic Prefix Insertion for Ifft
1599
Pre-Multiplication Processing Support in the Eftpe
1600
Post-Multiplication Processing Support in the Eftpe
1603
One-Shot' Initialization of the Pre/Post Multiplication Buffers
1605
Scalar Post Multiplication in Eftpe
1606
Frequency Correction Support During BD Repeat
1608
Pilot Symbols Generation and Spreading
1609
Scrambling Code Generation
1610
Code Generation with BD Repeat
1611
Code Generation Status
1612
Inverse Transform Processing
1616
Eftpe Internal Scaling Calculations
1617
Scaling During Internal Radix Calculations
1618
User Defined Scaling
1619
Overall Scaling Amount Programming
1620
Input Exponent
1621
Adaptive Input Scaling
1622
Extra Scaling
1623
Eftpe Configuration Register
1624
Data Size Registers
1625
Eftpe ECC Support
1626
DEPE Buffer Descriptors and Header Structures
1627
LH] Indication in DEPE Header
1628
Input Buffer Offset Support (3GLTE and UMTS Only)
1629
DEPE Processing
1630
Add Filler Bits
1631
Wimax Processing (802.16E)
1634
Randomization
1635
Wimax Processing (802.16M)
1637
Bit Collection
1638
UMTS Processing
1639
CRC Calculation
1640
Rate Matching
1641
Bit Collection
1643
UMTS Processing Summary
1645
DEPE Output Data Structure
1647
Output Data Structure for Multiple Tasks
1650
Separate Vectors Output Data Structure for UMTS
1651
BD Status Indications
1652
CRPE Uplink/Downlink UMTS Chip Rate Processing Operation
1653
CRPE-ULB Parameters Initialization
1654
CRPE-ULB Core Descriptors Initialization
1655
Interpolation Mode
1656
One Output Buffer Mode
1658
CRPE-ULB Data Organization
1660
Core Descriptors and Command List Size Table
1662
Finger Commands
1663
Bytes Finger Command Size
1664
Interpolation Modes
1665
Internal Interpolation Antenna Input Data Structure (INT_MODE = 1)
1666
Antenna Input Sub Slot Data Structure (All Modes)
1669
Internal Interpolation Processing Implementation
1670
Interpolation X16: INT_MODE = 1
1671
Interpolation X4: INT_MODE = 1
1672
Interpolation Saturation During Internal Interpolation
1673
Scrambling Data Offset
1674
Descrambling Using Long Codes
1675
Descrambling Using Short Codes
1676
Despreading
1677
FC Bypass Mode
1679
Output Buffer Capacity
1680
Output Buffer Data Structure
1682
System Output Buffers Structure
1685
Compressed Mode (ODT = 0X3)
1686
Finished Channel Search
1687
Finished Channel Search Limitations
1688
Chip Rate Uplink Fast Operation
1690
CRPE-ULF Configuration Registers Initialization
1691
CRPE-ULF Delay Spread Modes
1692
CRPE-ULF Functional Description
1693
Time Synchronization
1695
Direct Mode
1696
Input Data Interface—Interpolation Bypass Mode
1697
Interpolation Bypass Initialization
1699
Despreading and Descrambling (DD)
1700
Physical Channel (PCH) and Slot Format (SLF) Selection
1701
Scrambling Sequence Generation
1702
OVSF Code Generation
1703
DPCCH/PRACH PILOT Correlation
1706
E-DPCCH and HS-DPCCH Data Correlation
1707
Updating Finger Offset
1709
Compressed Pchs
1711
Soft Symbol Packet Header
1712
System Memory Output Buffers Structure
1713
Writing the Output Data Results
1714
Finger Command (FIC) Structure
1715
Physical Channel Command Structure (PCHC)
1716
Command Fetching Description
1719
Command Generation Restrictions
1720
CRPE-ULF Errors
1721
CRPE-ULF Initialization
1722
CRPE Downlink Operation Overview
1723
CRPE-DL Input Data Structure
1727
Internal CRPE Operation
1728
TPC Value Override
1729
STTD Encoding
1730
Scrambling Operation
1731
Gains Usage Synchronization
1732
Combine Operation
1733
Beam Forming Operation
1734
Virtual Antennas Idle Period
1736
CPRI Output Mode
1737
Output Buffer Accesses Constraints
1738
Initialization of CPRI Output Mode
1739
CRPE-DL Rate Control
1740
CRC Operation
1741
Byte Reverse CRC Processing
1743
CRC Polynomials
1744
Inverse Output Operation
1745
Code Generation Operation
1746
Uplink Scrambling Codes Generation
1747
Short Complex Scrambling Codes Generation
1749
Downlink Scrambling Codes Generation
1751
Code Generation Offset
1753
CONVPE Convolution and Correlation Processing Operation
1754
CONVPE Programming
1755
RACH Preamble Task Limitations
1756
RACH Preamble Input Data Structure - Antenna Data
1757
RACH Preamble Input Data Structure - Signatures
1758
Path Searcher Correlations Descriptor
1759
CONVPE Path Search Task Limitations
1760
FDU Processing
1761
FDU Operation
1762
FDU Arithmetic Scheme
1763
FDU Scaling
1764
Operation Flow
1766
MAPLE-B2 Internal Task Control
1768
MAPLE-B2 Power Gating Scheme
1769
Reset
1771
MAPLE-B2 Programming
1775
General Programming Guidelines
1776
MAPLE Mode Configuration 1 Parameter (MMC1P)
1778
MAPLE Etvpe Configuration Parameter (MTVCP)
1781
CRPE-DL Output Mode Configuration Parameter (CDOMCP)
1782
CRPE-ULB Mode Configuration Parameter (CRUBMCP)
1784
Parameter RAM
1785
MAPLE Ucode Version Parameter (MUCVP)
1787
MAPLE Timer Period Parameter (MP_TPP)
1788
MAPLE Clock Gating Control Parameter (MCGCP)
1789
Etvpe Parameter RAM Description
1790
Parameter (Mtvpvxhcp)
1791
Parameter (Mtvpvxlcp)
1792
Parameter (Mtvppcyp)
1793
Parameter (Mtvpvsxc0P)
1794
Parameter (Mtvpvsxc1P)
1795
Eftpe Parameter RAM Description
1796
Eftpe Data Size Set X Parameter 0 (Ftpedssxp0)
1797
Eftpe Data Size Set X Parameter 1 (Ftpedssxp1)
1798
Eftpe Data Size Set X Parameter 2(Ftpedssxp2)
1799
Parameter (Ftpexuprmbpp)
1800
Parameter (Ftpexupsmbpp)
1801
Eftpe X Update Buffers Size Parameter (Ftpexubsp)
1802
Eftpe Complete Update Buffers Routine Parameter (FTPECUBRP)
1803
CRPE Parameter RAM Descriptions
1804
CRPE-ULB Parameters Description
1805
Configuration Parameter (Mcubpchxobicp)
1809
MAPLE CRPE-ULB Configuration Parameter (MCUBCP)
1815
CRPE-ULF Parameters Description
1818
MAPLE CRPE-ULF General Configuration Parameter (MCUFGCP)
1823
CRPE-DL Parameters Description
1826
MAPLE CRPE-DL Slot Channel <X> Parameter 0 (Mcdlscxp0)
1827
MAPLE CRPE-DL Slot Channel <X> Parameter 1 (Mcdlscxp1)
1828
MAPLE CRPE-DL Slot Channel <X> Parameter 2 (Mcdlscxp2)
1829
MAPLE CRPE-D1L Fast Channel <X> Parameter 0 (Mcdlfcxp0)
1831
MAPLE CRPE-DL Fast Channel <X> Parameter 1 (Mcdlfcxp1)
1832
MAPLE CRPE-DL Slot Channel <X> Parameter 2 (Mcdlscxp2)
1834
MAPLE CRPE-DL Output Buffer <X> Size Parameter (Mcdlobxsp)
1837
MAPLE CRPE-DL General Configuration Parameter (MCDLGCP)
1840
Serial Rapidio Doorbell Support Attributes Parameters
1841
Hardware Semaphore Port 1 Base Address Parameter (HSP0BAP)
1843
Hardware Semaphore Port 2 Base Address Parameter (HSP1BAP)
1844
MAPLE-B Doorbell General Configuration Parameter (MDGCP)
1846
MAPLE BD Rings Configuration Parameter 0 (MBDRCP0)
1849
MAPLE BD Rings Configuration Parameter 1 (MBDRCP1)
1852
MAPLE BD Rings Configuration Parameter 2 (MBDRCP2)
1854
Etvpe Buffer-Descriptor Structure
1867
Eftpe Buffer Descriptor Structure
1878
Buffer Descriptor Special Notes
1887
Eftpe Buffer Descriptor's Extension
1888
Transform Length Encoding
1893
DEPE BD and Header Structures
1894
Buffer Descriptors Notes
1902
DEPE Headers Structure
1903
DEPE Header Structure for Wimax (802.16E)
1905
DEPE Header Structure for Wimax (802.16M)
1907
DEPE Header Structure for UMTS
1909
CRPE-ULB Core Descriptor, Finger and PCH Commands Structures
1912
CRPE-ULB Core Descriptors
1913
CRPE-ULB Finger Command Structure
1914
CRPE-ULB PCH Command Structure
1916
CRCPE Buffer Descriptor Structure
1919
CGPE Buffer Descriptor Structure
1924
CONVPE Buffer Descriptor Structure
1928
CONVPE RACH Preamble Correlations Task Descriptor
1929
CONVPE Path Searcher Task Descriptor
1933
Registers
1939
PSIF PIC Event Register 0 (PSPICER0)
1941
PSIF PIC Event Register 1 (PSPICER1)
1942
PSIF PIC Event Register 2 (PSPICER2)
1943
PSIF PIC Edge/Level Register 0 (PSPICELR0)
1945
PSIF PIC Mask Register 0 (PSPICMR0)
1946
PSIF PIC Mask Register 1 (PSPICMR1)
1947
PSIF PIC Mask Register 2 (PSPICMR2)
1948
PSIF PIC Interrupts Assertion Clocks Register (PSPICIACR)
1950
Etvpe Registers Description
1951
Etvpe Aposteriori Quality Configuration Register (TVAQCR)
1952
Eftpe_X Registers Description
1953
Eftpe_<X> Data Size Register 0 (Ftpe<X>Dsr0)
1954
Eftpe_<X> Data Size Register 1 (Ftpe<X>Dsr1)
1955
Eftpe_<X> Data Size Register 2 (Ftpe<X>Dsr2)
1956
Eftpe_<X> Configuration Register (Ftpe<X>Cr)
1957
Eftpe_<X> ECC Interrupt Status Register (Ftpe<X>Eccisr)
1958
CRPE-ULB Registers Description
1960
CRPE-ULB Event Status Register (CRUBESR)
1964
CRPE-ULF Registers Description
1966
ULF General Configuration Register (ULFGCR)
1967
ULF Secondary Configuration Register (ULFSCR)
1969
ULF Output Buffer <X> Base Configuration Register (Ulfobxbcr)
1971
ULF Event Status Register (ULFESR)
1973
ULF Command FIFO Status Register (ULFCFSR)
1974
ULF Input Buffer Status Register (ULFIBSR)
1975
ULF ECC Status Register (ULFECCSR)
1976
CRPE-DL Registers Description
1977
CRPE-DL Chips Output Data Table (CDCODT)
1978
CRPE-DL Slot Format Look-Up Table (SFLUT)
1980
CRPE-DL Scrambling Initialization Look-Up Table (SCRILUT)
1983
CRPE-DL Normalization Value Configuration Register (CDNVCR)
1985
CRPE-DL Virtual Antenna Gains Control Register 0 (CDVAGLR0)
1986
CRPE-DL Virtual Antenna Gains Control Register 1 (CDVAGLR1)
1987
CRPE-DL Start Control Register (CDSLR)
2004
CRPE-DL TPC Command Control Register (CDTCLR)
2005
Ter (CDVAGCLR)
2006
CRPE-DL General Command Control Register (CDGCLR)
2007
CRPE-DL Idle Period Control Register <X> (Cdiplrx)
2009
CRPE-DL Rate Control Register (CDRLR)
2012
CRPE-DL Event Status Register (CDESR)
2013
CRPE-DL Processing Stage Status Register (CDPSSR)
2014
CRPE-DL ECC Status Register (CDECCSR)
2015
Architecture Overview
2018
Functional Diagram
2020
Controller
2021
Channel-Controlled Access
2022
Polychannel
2023
Virtual Channels
2024
Channel Completion
2025
Common EU Interface
2026
Bus Transfers
2027
System Bus Master Read
2028
Controller Interrupts
2029
Controller Secondary Interrupt
2030
Polychannel
2031
Channels
2032
Arbitration Among Channels
2033
Arbitration for Use of the Controller
2034
Arbitration Algorithms
2035
Channel Registers and Structures
2036
Channel Done Interrupt
2037
Descriptors and Link Tables
2038
Execution Units
2040
Public Key Execution Unit (PKEU)
2042
PKEU Reset Control Register
2043
PKEU End_Of_Message Register
2044
CLEARMEMORY: Clear Memory (0X01)
2046
MOD_EXP_TEQ: Exponentiate Mod N and Deconvert from Montgomery Format with Timing Equalization (0X1D)
2047
Point Multiply in Affine Coordinates (0X05)
2048
Point Multiply in Projective Coordinates (0X07)
2049
Point Multiply in Projective Coordinates (0X08)
2050
Coordinates (0X09)
2051
Projective Coordinates (0X0B)
2052
MOD_RED: Prime Field (Fp) Modulo Reduction (0X12)
2054
RSA_SSTEP: RSA Single Step Modular Exponentiation (0X80)
2056
Timing Equalization (0X1E)
2057
Data Encryption Standard Execution Unit (DEU)
2058
DEU Status Register
2059
DEU IV Register
2060
Advanced Encryption Standard Execution Unit (AESU)
2061
AESU Data Size Register
2062
AESU Interrupt Mask Register
2063
Context for CBC, CBC-RBP, OFB, and CFB128 Cipher Modes
2065
Context for Counter (CTR) Cipher Mode
2066
Context and Operation for XCBC-MAC Cipher Mode
2068
Context and Operation for GCM-GHAS Cipher Mode
2069
Context and Operation for CMAC (OMAC1) Cipher Mode
2070
Context for CCM Cipher Mode
2072
Context and Operation for GCM Cipher Mode
2074
AESU Key Registers
2082
Message Digest Execution Unit (MDEU)
2083
MDEU Mode Register
2084
MDEU Key Size Register
2085
MDEU Reset Control Register
2086
MDEU Interrupt Mask Register
2087
MDEU Key Registers
2088
ARC Four Execution Unit (AFEU)
2089
AFEU Key Size Register
2090
AFEU Reset Control Register
2091
AFEU Context
2092
AFEU Key Registers
2093
KEU Mode Register
2094
KEU Reset Control Register
2095
KEU Interrupt Mask Register
2096
KEU Icv_In Register
2097
KEU Key Data Registers _[3–4] (Integrity Key)
2098
Cyclic Redundancy Check Unit (CRCU)
2099
CRCU Mode Register
2100
CRCU Interrupt/Error Status Register
2101
CRCU Key Register
2102
Crcu Fifo
2103
STEU Mode Register
2104
STEU Interrupt Status Register
2105
STEU Icv_In Register
2107
STEU Context Registers
2108
Random Number Generator (RNGU)
2109
RNGU Mode Register
2110
RNGU Interrupt Mask Register
2111
Programming Model
2112
Descriptors and Link Tables
2116
Descriptor Header
2118
Descriptor Types
2120
Descriptor Formats
2122
Descriptor Operations During Cryptographic Processing
2124
Descriptor Types 0000_0: Aesu_Ctr_Nonsnoop
2127
Descriptor Type 0001_0: Common_Nonsnoop
2128
Descriptor Type 0010_0: Hmac_Snoop_No_Afeu
2133
Descriptor Type 0101_0: Common_Nonsnoop_Afeu
2139
Descriptor Type 1000_0: Pkeu_Mm
2140
Descriptor Type 1100_0: Hmac_Snoop_Aesu_Ctr
2142
Descriptor Type 0000_1: Ipsec_Esp
2144
Ipsec-ESP Inbound
2146
Descriptor Type 0001_1: IEEE 802.11I_Aes_Ccmp
2148
IEEE 802.11I Outbound
2149
IEEE 802.11I Inbound
2152
Descriptor Type 0010_1: SRTP
2154
SRTP Outbound
2155
SRTP Inbound Without ICV Compare
2157
SRTP Inbound with ICV Compare
2159
Pkeu_Ptadd_Dbl
2160
Descriptor Type 1000_1: Tls_Ssl_Block
2164
TLS / SSL Block Cipher Outbound
2165
TLS / SSL Block Cipher Inbound
2167
Descriptor Type 1001_1: Tls_Ssl_Stream
2170
TLS / SSL Stream Cipher Outbound
2171
TLS / SSL Stream Cipher Inbound
2173
Descriptor Type 1010_1: Raid_Xor
2175
Descriptor Type 1011_1: Aes_Gcm
2177
AES_GCM Outbound for Macsec
2181
AES_GCM Inbound for Macsec
2183
AES_GCM Outbound for Ipsec
2185
AES_GCM Inbound for Ipsec
2187
Descriptor Type 1100_1: Dbl_Crc
2188
Iscsi Dbl_Crc Inbound
2190
Pointers
2191
Link Tables
2193
SEC Controller
2195
Controller Identification Register (CIDR)
2198
EU Assignment Status (EUASR)
2199
Controller Interrupt Enable Register (CIER)
2201
Controller Interrupt Status Register (CISR)
2205
Controller Interrupt Clear Register (CICR)
2208
Polychannel
2210
Fetch FIFO Enqueue Counter (FFEC)
2211
Descriptor Finished Counter (DFC)
2212
Data Bytes in Counter (DBIC)
2213
Data Bytes out Counter (DBOC)
2214
Channel Configuration Registers for Channels 1–4 (CCR[1–4])
2215
Channel Status Registers (CSR[1–4])
2218
Current Descriptor Pointer Register (CDPR)
2223
Channel Fetch FIFO (CFF)
2225
Channel Descriptor Buffer (DB)
2226
PKEU Registers
2227
PKEU Key Size Register (PKEUKSR)
2229
PKEU AB Size Register (PKEUABSR)
2230
PKEU Data Size Register (PKEUDSR)
2231
PKEU Reset Control Register (PKEURCR)
2232
PKEU Status Register (PKEUSR)
2233
PKEU Interrupt Status Register (PKEUISR)
2234
PKEU Interrupt Mask Register (PKEUIMR)
2236
PKEU End_Of_Message Register (PKEUEOMR)
2237
PKEU Parameter Memory B
2238
DEU Registers
2239
DEU Key Size Register (DEUKSR)
2240
DEU Data Size Register (DEUDSR)
2241
DEU Reset Control Register (DEURCR)
2242
DEU Status Register (DEUSR)
2243
DEU Interrupt Status Register (DEUISR)
2244
DEU Interrupt Mask Register (DEUIMR)
2246
DEU End_Of_Message Register (DEUEOMR)
2248
DEU Key Registers (DEUKR[1–3])
2249
AESU Registers
2250
AESU Key Size Register (AESUKSR)
2253
AESU Data Size Register (AESUDSR)
2254
AESU Reset Control Register (AESURCR)
2255
AESU Status Register (AESUSR)
2256
AESU Interrupt Status Register (AESUISR)
2257
AESU Interrupt Mask Register (AESUIMR)
2259
AESU ICV Size Register (AESUICVSR)
2261
AESU End_Of_Message Register (AESUEOMR)
2262
AESU Context Registers (AESUCR[1–12])
2263
AESU Key Registers (AESUK[U/L]R[1–3])
2266
AESU Fifos
2267
MDEU Registers
2268
MDEU Key Size Register (MDEUKSR)
2270
MDEU Data Size Register (MDEUDSR)
2271
MDEU Reset Control Register (MDEURCR)
2272
MDEU Status Register (MDEUSR)
2273
MDEU Interrupt Status Register (MDEUISR)
2274
MDEU Interrupt Mask Register (MDEUIMR)
2276
MDEU ICV Size Register (MDEUICVSR)
2278
MDEU End_Of_Message Register (MDEUEOMR)
2279
MDEU Context Registers (MDEUCR)
2280
MDEU Key Registers (MDEUKR[1–8])
2282
AFEU Registers
2283
AFEU Key Size Register (AFEUKSR)
2284
AFEU Context/Data Size Register (AFEUCDSR)
2285
AFEU Reset Control Register (AFEURCR)
2286
AFEU Status Register (AFEUSR)
2287
AFEU Interrupt Status Register (AFEUISR)
2288
AFEU Interrupt Mask Register (AFEUIMR)
2290
AFEU End_Of_Message Register (AFEUEOMR)
2292
AFEU Context Memory Pointer Register (AFEUCMPR)
2293
KEU Registers
2294
KEU Key Size Register (KEUKSR)
2296
KEU Data Size Register (KEUDSR)
2297
KEU Reset Control Register (KEURCR)
2298
KEU Status Register (KEUSR)
2299
KEU Interrupt Status Register (KEUISR)
2300
KEU Interrupt Mask Register (KEUIMR)
2302
KEU Data out Register (KEUDOR) for F9 MAC
2304
KEU End_Of_Message Register (KEUEOMR)
2305
KEU IV1 Register (KEUIV1R)
2306
KEU Icv_In Register (KEUICVIR)
2307
KEU IV2 Register (KEUIV2R)
2308
KEU Context 1–6 Registers (KEUCR[1–6])
2309
KEU Key Data Registers 1–2 (KEUKDR[1–2])
2310
KEU Key Data Registers 3–4 (KEUKDR[3–4])
2311
CRCU Registers
2312
CRCU Key Size Register (CRCUKSR)
2314
CRCU Data Size Register (CRCUDSR)
2315
CRCU Reset Control Register (CRCURCR)
2316
CRCU Control Register (CRCUCR)
2317
CRCU Status Register (CRCUSR)
2318
CRCU Interrupt/Error Status Register (CRCUISR)
2319
CRCU Interrupt/Error Mask Register (CRCUIMR)
2321
CRCU ICV Size Register (CRCUICVSR)
2323
CRCU End_Of_Message Register (CRCUEOMR)
2324
CRCU Context Register (CRCUCXR)
2325
CRCU Key Register (CRCUKR)
2326
STEU Registers
2327
STEU Key Size Register (STEUKSR)
2328
STEU Data Size Register (STEUDSR)
2329
STEU Reset Control Register (STEURCR)
2330
STEU Status Register (STEUSR)
2331
STEU Interrupt Status Register (STEUISR)
2332
STEU Interrupt Mask Register (STEUIMR)
2334
STEU Data out Register (STEUDOR) for F9 MAC
2336
STEU End_Of_Message Register (STEUEOMR)
2337
STEU IV1 Register (STEUIV1R)
2338
STEU Icv_In Register (STEUICVIR)
2339
STEU IV2 Register (STEUIV2R)
2340
STEU Context Register 1 (STEUCR1)
2341
STEU Context Register 2 (STEUCR2)
2342
STEU Context Register 3 (STEUCR3)
2343
STEU Context Register 4 (STEUCR4)
2344
STEU LFSR State Registers 0–7 (STEULFSRSR[0–7])
2345
STEU FSM State Registers 1 (STEUFSMSR1)
2346
STEU FSM State Register 2 (STEUFSMSR2)
2347
STEU Key Data Registers 1–2 (STEUKDR[1–2])
2348
RNGU Registers
2349
RNGU Data Size Register (RNGDSR)
2350
RNGU Reset Control Register (RNGRCR)
2351
RNGU Status Register (RNGSR)
2352
RNGU Interrupt Status Register (RNGISR)
2353
RNGU Interrupt Mask Register (RNGIMR)
2354
RNGU End_Of_Message Register (RNGEOMR)
2356
RNGU Output FIFO
2357

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